Fpga uart Tx, a simple FPGA serial transmission module

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// UART sending module, baud rate 9600 // Chen Peng // 20120118 module uart_tx (sys_clk, // system clock input reset_n, // Asynchronous Reset input Tx, // data line txdata, // The tx_start data line for data transmission, // start the tx_state of the sending signal // The status of the transmitter); inputsys_clk, reset_n, tx_start; input [7: 0] txdata; outputtx, tx_state; reg Tx, tx_state; parameter sys_clk = 20000000; // system clock parameter tx_clk = 9600; // 9600 bpsparameter txdata_w = 12; // baud rate clock generator frequency division register bit width parameter txclk_data = sys_clk/tx_clk-1; // baud rate divider clock frequency division value // baud rate clock generator Reg [TxDATA_W-1: 0] clk_cnt; regen_txclk; // enable send clock wiretx_clk; // send baud rate clock always @ (posedge sys_clk or negedge reset_n) if (! Reset_n) clk_cnt <= 12 'd0; else if (! En_txclk) // do not need to enable the clock clk_cnt <= 12 'd0; else if (clk_cnt = txclk_data) clk_cnt <= 12 'd0; elseclk_cnt <= clk_cnt + 1 'b1; assign tx_clk = (clk_cnt = 0); // generates the receiving clock // The sending control state machine Reg [3: 0] txstate; Reg [7: 0] txtemp; // store the data to be sent by always @ (posedge sys_clk or negedge reset_n) if (! Reset_n) begintxstate = 4 'd0; txtemp = 8 'd0; tx_state = 1' B0; en_txclk = 1' B0; endelse if (txstate = 0) & (tx_state = 0) & tx_start) Begin // if the bus is idle and the start signal exists, en_txclk <= 1 'b1; // enable the send clock txstate <= 4'd1; // start to send the first status tx_state <= 1' D1; // send the busy txtemp <= txdata; // load the data to be sent endelse if (tx_clk) inincase (txstate) // synthesis full_case4 'd1: Begin // The sending start TX <= 1 'b0; txstate <= 4'd2; end4'd2: Begin // send bit0tx <= txtemp [0]; txstate <= 4'd3; end4' D3: begin // send bit1tx <= txtemp [1]; txstate <= 4'd4; end4'd4: Begin // send bit2tx <= txtemp [2]; txstate <= 4'd5; end4'd5: Begin // send bit3tx <= txtemp [3]; txstate <= 4'd6; end4' D6: begin // send bit4tx <= txtemp [4]; txstate <= 4 'd7; end4' D7: Begin // send bit5tx <= txtemp [5]; txstate <= 4'd8; end4'd8: Begin // send bit6tx <= txtemp [6]; txstate <= 4'd9; end4'd9: begin // send bit7tx <= txtemp [7]; txstate <= 4 'd10; end4' D10: Begin // send the parity bit and send the Tx <= 1 'b0; txstate <= 4'd11; end4'd11: Begin // send stop bit, high level TX <= 1' B1; txstate <= 4'd0; // enter Idle State en_txclk <= 1' B0; // The sending baud rate clock stops at tx_state <= 1' D0; // The sending logic idle endcaseend // end else ifendmodule