FPGA Configuration method

This paper introduces the difference of three modes under as, PS and Jtag.

As mode: Burned to the FPGA configuration chip saved, FPGA device every time the power up, as a controller from the configuration device EPCs actively emit read data signal, so that the EPCs data read into the FPGA, to achieve the FPGA programming, the method is applicable to the occasion does not need to upgrade frequently;

PS Mode: EPCs as a control device, the FPGA as a memory, the data written to the FPGA, to achieve the FPGA programming. can adopt micro-controller (SCM, ARM, etc.) or CPLD, this mode can be realized on-line FPGA programmable, easy to upgrade;

JTAG: Directly burned into the FPGA, because it is SRAM, power off to re-burn, suitable for debugging;

. pof files can be downloaded by as mode;

. sof files or converted. JIC can be downloaded via JTAG.

The USB blaster Download line supports the above three modes. (Http://baike.baidu.com/link?url=qmMniuXETFfL3zzXWhJYCDzAA4x0nVTKfkMGYMg7laPPhYqiYrY8ydGkibSYgf3PFlS-76m2C-istSaQtw5iCK)

When the FPGA is working properly, its configuration data is stored in SRAM and must be re-downloaded when power is added. In an experimental system, a computer or a controller is usually used for debugging, so PS can be used. In the practical system, in most cases, the FPGA must be actively guided to configure the operation process, when the FPGA will actively from the peripheral dedicated storage chip to obtain configuration data, and this chip in the FPGA configuration information is designed by the ordinary programmer in the POF format of the file into.

1. JATG mode

Jtag interface is an industry standard interface, mainly used for chip testing and other functions. Altera FPGAs can basically support JTAG commands to configure the way the FPGA is configured, and the JTAG configuration is higher priority than any other method. The JTAG interface has 4 required signal TDI, TDO, TMS and TCK as well as 1 optional signal trst consisting of:

. TDI for the input of test data;

. TDO, used to test the output of the data;

. TMS, the mode control pin, decides the jump of the tap state machine inside the JTAG circuit;

. TCK, test clock, other signal lines must be synchronized with it;

. TRST, optional, if the JTAG circuit is not used, it can be said to connect to GND.

The user can use Altera's download cable or use a smart device such as a microprocessor to set up the FPGA from the Jtag interface. Nconfig, MESL, and DCLK signals are used in other configuration modes. If you use only JTAG configuration, you need to pull the nconfig high, pull the Msel into any mode that supports JTAG, and pull the dclk to a high or low fixed level.

FPGA and 10-pin socket Connection diagram:

2. As (active serial) mode

Guided configuration operation by the FPGA device, which controls the external memory and initialization process, the EPCs series. For example, the EPCS1,EPCS4 configuration device is dedicated to the as mode and currently only supports the Stratix II and Cyclone series. This is done using the Altera serial configuration device. The cyclone device is in the active position and the configuration device is in a subordinate position. The configuration data is fed into the FPGA via the DATA0 pin. The configuration data is synchronized on the DCLK input and 1 clock cycles transmit 1 bits of data.

The As configuration device is a nonvolatile, flash memory-based memory that allows the user to program the configuration chip using Altera's Byteblaster II load cable, Altera's "Altera programming unit", or a third-party programmer. It interfaces with the FPGA for the following simple 4 signal lines:

. Serial clock input (DCLK): is generated by an oscillator (oscillator) inside the FPGA in configuration mode, which is switched off after the configuration is complete. The working clock is around 20MHz, while the fast as mode (Stratix II and Cyclone II support this configuration), the DCLK clock is operating around 40MHz, in the Altera active serial configuration chip, Only the dclk of EPCS16 and EPCS64 can support only 20MHz for 40MHZ,EPCS1 and EPCS4.

. As control signal input (ASDI);

. Chip selection signal (NCS);

. Serial data output.

FPGA and serial configuration chip connection diagram:

FPGA, serial configuration chip and 10-pin socket connection Figure 1:

FPGA, serial configuration chip and 10-pin socket connection Figure 2:

3. PS (passive serial) mode

PS (passive serial) is an external computer or controller that controls the configuration process and is one of the most used configuration methods. This configuration mode is supported by all Altera FPGAs. Complete with configuration devices such as Altera's download cables, enhanced configuration devices (EPC16,EPC8,EPC4), or smart hosts such as microprocessors and CPLD, during the PS configuration, The configuration data is stored externally from the components (these can be Altera configuration devices or other flash devices on the veneer) and fed into the FPGA via the DATA0 pin. Configuration data on the DCLK rising edge latch, 1 clock cycles transmit 1 bits of data.

Signal interface to FPGA:

. DCLK (configuration clock);

. DATA0 (configuration data);

. Nconfig (Configuration command);

. Nstatus (State signal);

. Conf_done (Configuration completion indication).

In PS mode, the FPGA is in a completely passive position. The FPGA receives the configuration clock, configuration command and configuration data, gives the configured status signal, and configures the completion indication signal. The PS configuration can use Altera's configuration device (EPC1, EPC4, etc.), can use the microprocessor in the system, or use the CPLD on a single board, or Altera's download cable, regardless of where the configured data source comes from, as long as the FPGA needs to simulate the configuration timing, Writing configuration data to the FPGA is possible.

After power-up, the FPGA detects a low-to-high hop edge on the nconfig pin, so the configuration process can be started automatically.

(1) Depending on the mode, theMsel has different settings .

(2) configuration chip EPCS16 storage size is 16MBITS=2MB.

(3) The configuration of the Board of the laboratory JAG mode and "as mode", but there is no as configuration port, the SOF file to convert my Jic file, using JATG to download the configuration file to the configuration chip. Therefore, this method can be called pseudo as mode.

The serial port configuration chip EPCS16 4 pins (DATA, DCLK, NCS and ASDI) connected to the FPGA, Jtag Port connection mode as described above. The Msel is only three bits and is configured as 010 (as mode), where it is connected as mode.

This method of using JTAG to download the configuration file configuration chip is as follows:

The JTAG interface and as interface are linked by serial flash loader design. See the C3 Manual "programming Serial Configuration Devices in-system Using the JTAG Interface" section. Of course, you can also keep both as and Jtag, as described in the "combining JTAG and Active Serial Configuration schemes" section.

Have the following issues:

1. JTAG Port 4 foot and 6 foot connection is not understood. 4 feet According to the manual as follows, then it should be Vcca (analog), rather than the design of VCC (number). Learn FPGA power design!

and 6 feet According to the manual as follows, then should be not connected bar, the design even VCC.

2. Although Nconfig, Nstatus, Config_done and external arm connection, but Data[0], DCLK is not connected with arm, so the project PS mode through ARM configuration FPGA, I do not know if such a connection can be implemented as mode remote update??

Answer: There should be a design problem.

Reference: Http://bbs.ednchina.com/BLOG_ARTICLE_1796890.HTM,http://blog.sina.com.cn/s/blog_7d1e2bb101016w1n.html,

ARM dynamic Configuration fpga:http://wenku.baidu.com/link?url=ib6wraiz5g32fjerwgic4vbqt5wg5fohfy9awcpmjauqiqhppcjwtcgxdm3g580_ xi9llrtyzwubcxnom-jc04nm884medo0paaedcjgp7c

FPGA Configuration method