FPGA Implementation and Driver Design of PCI bus protocol

At present, many companies have proposed new types of computer high-speed bus, such as the Arapahoe bus standard and hypertransport technology. However, the protocols are not compatible with each other and there is no unified standard. As a traditional universal local bus, PCI bus still occupies the mainstream PC market, with tenacious vitality.

　　

There are various PCI interface chips on the market, such as AMCC's S5933 and PLX's 9080 series. The dedicated chip can implement the complete interface functions between the PCI master device and the slave device mode, and convert the complex PCI bus interface into a relatively simple user interface. However, the system structure is limited by the interface chip, the target system cannot be flexibly designed and the cost is high. In this paper, the PCI interface logic is designed with an FPGA chip that conforms to the PCI electrical characteristics, and the interface function of the 33 MHz and 32-bit data width PCI slave device module is realized, it saves the system's logical resources and can integrate other user logic into the same chip, reducing costs and increasing design flexibility. In addition, a device driver under Windows 9x is provided, which can interface with the application to form a complete system. At present, the system has been used by printing and dyeing enterprises in data collection and processing.

　　

1. system composition and function description

　　

The overall system diagram 1 is shown.

As shown in figure 1, the hardware platform of the system is a PCI Card. The structure of this card is very simple, mainly composed of FPGA chip, RAM chip and output interface. The FPGA chip integrates the PCI interface module and data processing module. The PCI interface module provides interfaces with a MHz working clock and a 32-bit bus width. It supports read/write and PCI interrupt functions in I/O space, memory space, and configuration space. Because the simplified PCI interface occupies less logical resources, other user logic can be integrated into the same chip. As an application example, this article adds a data processing module that processes the data transmitted by the PCI interface and outputs the data to the lower computer through the output interface. The RAM chip provides the cache function for data processing.

　　

2. Simplified PCI protocol implementation in device Mode

　　

To implement basic functions of the PCI interface, you must complete the following modules:

　　

(1) PCI configuration space settings. The PCI protocol supports three address spaces: I/O space, memory space, and configuration space. The configuration space is required to support automatic configuration of PCI devices.

　　

(2) PCI slave device state machine. A pci bus state machine is a state stream of a computer system with a PCI bus. It is a description of the condition and time sequence from one known state to another. This is the most basic and important part in the PCI interface design.

　　

(3) address decoding and command decoding. Address decoding is used to determine whether the PCI device should respond to the operation of the current bus. Command decoding is used to indicate that the PCI device performs the corresponding action according to different bus commands.

　　

This article uses the MAX + pluⅱ software platform of Altera, and the hardware description language uses the Altera HDL language, which can also be easily converted to the VHDL or VerilogHDL language. Before that, the definition of PCI bus signal is introduced.

　　

2.1 bus signal Definition

　　

Based on PCI Bus Protocol Version 2.2, the PCI interface in device mode contains at least 47 pins. Figure 2 shows the distribution of pins by function, with the required pins on the left and the optional pins on the right. For the sake of simplicity, the following pins are used in this article. Other pins do not enable or set to high-impedance mode.

(1) The MHz Synchronous Clock signal CLK provided by the system and the reset signal rst # (# indicates that the low level is effective );

　　

(2) Core signal about data transmission: 32-bit address/Data multiplexing line ad [31: 0], bus command/byte enable multiplexing line C/be [] # And even verification signal par;

　　

(3) interface control signals frame #, trdy #, irdy #, stop #, devsel #, and idsel. Frame # indicates the start and end signals of data transmission, trdy # prepares signals for the master device, irdy # prepares signals for the slave device, and stop # indicates the stop request signal of the slave device, devsel # select a signal for the device, and idsel is the chip selection signal for configuring null read/write;

　　

(4) interrupt pin INTA #. To simplify the PCI protocol, this article only implements the most important bus commands. Table 1 provides the supported bus commands corresponding to the C/be [] # encoding value. 2.2 configure space settings

The configuration space is 256 bytes. The first 64 bytes are required. The basic information of the PCI device is recorded. The following are important:

　　

(1) vendorid, DeviceID, and class code fields: Indicate the manufacturer, device number, and type of the device, respectively;

　　

(2) command and status fields: the control commands and the current status of the PCI device are provided;

　　

(3) Base adress register domain: indicates whether the PCI device reads and writes data in the I/O or memory mode and the size of the required address space;

　　

(4) interrupt line and interrupt pin fields: Specify the interrupt number and pin used by the device respectively. In access to the configuration space, use AD [] to address a dual DWORD. In this design, the configuration space settings are shown in Table 2. For more information about the meanings of each value, see [1].

 

2.3 simplified slave device state machine

　　

In the PCI protocol, the standard slave device state machine contains five states, and the jump conditions of each State are complex. This article simplifies the slave device state machine without violating the PCI protocol, as shown in 3.

 

　　

In Figure 3, status transfer condition signals a, B, and C are defined as follows: A indicates configuring space access conditions, and B indicates I/O space or memory space access conditions, c Represents the bus transmission start condition. The implementation of these three conditions is provided by the command decoding module.

　　

Idle is the default status of the system, indicating that the bus is currently idle. Generally, when a device is in the idle state, it must detect signals from the PCI bus and later-level devices so that the device can respond appropriately. When the device is in the s_data status, it completes the first data transmission and directly jumps to the backoff status unconditionally. The device transmits multiple data in the backoff status until the master device is disconnected. Note that when the IP address for sudden transmission of I/O space, configuration space, and memory space exceeds the range of device ing addresses, a stop signal must be established from the device in this status, disconnect access questions. When the frame signal is invalid or the transmission ends, the device returns to the initial idle status. Bus_busy is busy, indicating that the bus is being used by other devices. There are two transfer paths. If the bus is still in use, it stays in the bus_busy state; otherwise, idle is returned.

　　

2.4 address decoding and command decoding module

　　

The address decoding module checks whether the PCI address matches the base address of the PCI Card. You can compare the value on the signal line of AD [31: 00] With the set base address. If the PCI address falls within the set base address range, the PCI Card responds to the current bus operation.

　　

The command decoding module instructs the PCI Card to respond to different bus commands, and completes command decoding by checking the values on the C/be [] # signal line and comparing them with the bus commands listed in Table 1.

　　

3. Driver Design in Windows9x System

　　

For PCI devices, the driver provides functions such as obtaining the configuration space information of the PCI Card, removing PCI interruptions, and transmitting bus data. This article describes how to use numbench's VtoolsD software to design a driver.

　　

3.1 search for the PCI Card and read the configuration space information

　　

The configuration space contains the information required for the system to initialize the PCI device. First, you need to traverse the entire hardware tree to find the specified PCI device. For each device, compare its vendor ID and device ID. If it matches the information of the designed PCI card, it reads its configuration space information.

　　

3.2 read/write operations in I/O mode

　　

Read/write in I/O mode is relatively simple. After obtaining the base address of the PCI device, you can use the port read/Write Functions inpd and outpd in the C ++ language. Example:

　　

Temp = _ inpd (gbaseaddresses); // The data read from temp

　　

_ Outpd (gbaseaddresses data); // write data to the base address

　　

Gbaseaddresses is the base address value, and data is the data during the write operation.

　　

Read/write in 3.3 memory mode

　　

For read/write in the memory mode, an important problem is address ing. Because hardware devices read and write physical memory, but applications read and write virtual addresses, there is a problem of ing physical memory addresses to user program linear addresses.

　　

The ing function is completed by calling the standard library function of the VtoolsD software. Allocate the corresponding space in the system memory based on the given physical address and required space size. First, use the pagereserve function to allocate the linear address space of the current reserved page, and then use the service of the pagecommitphys function to allocate the corresponding physical address space for the starting linear address space. The procedure is as follows:

　　

Ulong npages = _ npages _ (physaddress sizeinbytes );

Linear = pagereserve (pr_system npages pr_fixed );

Pagecommitphys (pagenum (linear), npages pagenum (physaddress), pc_incr | pc_writeable | pc_user );

Linpagelock (pagenum (linear), npages 0 );

Here, physaddress is the given physical address, and sizeinbytes is the size of the required space.

　　

After the ing between physical Ram and system memory is established, you can use the file operation base class cfile class in C ++ to read and write data. First, open the file using the cfile member function open. To ensure data read and write accuracy, open the file in binary mode. Then, use the Read and Write member functions to read and write the file; close the file with the number of close member functions.

　　

3.4 suspension and handling of interruptions

　　

Initialize the interrupt in the on_device_init function. That is, the interrupt Number of the previously read PCI device is used, the vpicd_virtualize_irq function is used for the interrupt hook, and the vpicd_physically_unmask function is called to enable the interrupt.

　　

Rtcirqhandle = vpicd_virtualize_irq (& irqdesc );

Vpicd_physically_unmask (rtcirqhandle );

In the rtcint_handler function, you can perform various operations, such as sending a custom message to the application to notify the interruption.

　　

3.5 communications with Applications

　　

Generally, the application calls the VxD driver through the createfile function to obtain a VxD file handle. Use the following statement to open a file named mydriver. VxD and save the obtained handle to hvxd.

　　

Hvxd = createfile ("\\\\\ mydriver. VxD", 0, create-New, file-flag-delete-on-Close, 0 );

　　

The hvxd and deviceiocontrol functions can be used to transmit data with the driver.

　　

In this paper, the flex6000 series chip of Altera Company is used as the EPF6016TC144-3 to realize the simplified from the device mode PCI protocol, and implement the driver program design in Windows9x System. The entire system works well. Resource usage: 113 available I/O pins, 51 occupied, 45% occupied; 1320 available logical units, 151 occupied, 11% occupied.

　　

The simplified PCI protocol occupies a small amount of logical resources, allowing you to flexibly and conveniently add and improve functions. At the same time, you can integrate other user modules in the same chip to implement different functions, to reduce costs. At present, the system has been applied in data collection and processing, image processing and other aspects.