Hjr-fpga:verilog HDL Programming and Testbench design

First, the FPGA can do two types of chips, digital circuits and microprocessors

Microprocessors generally and SOPC on-chip systems (that is, the microprocessor and some on-chip peripherals are integrated into a chip) to do together, such as Nios-ii, and then again

Digital circuits are divided into:

Combinational logic circuits (circuits of various and/or non-gates, output depends only on current input), e.g. compiler code, adder

Sequential logic circuit (with memory function, trigger), such as counter, shifter, divider

Timing logic circuit is divided into synchronous and asynchronous, synchronous circuit has only one clock source, all triggers are triggered at the same time, asynchronous opposite, triggering time has successively

The commonly used digital circuit language has two kinds of VHDL and Verilog Hdl,verilog HDL use more also more simple, we first say Verilog HDL

First, the sequential circuit.

First, the Verilog HDL program structure

is divided into the module program and the test program (testbench), each module is instantiated after the program is a component, the test program is to all possible inputs are simulated again, view the results

Modular Program (module)

Module Test (X,Y,Z,S,CO)//module modules name (port 1, Port 2,......);
Input x,y;//inputs and outputs the port declares output
Z;
Wire S,co//wire reg and other types of variable declarations
Assign S = x&y//logic, function description
endmodule//end

Test file (testbench)

. Itimescale 1ns/100ps//A time unit 1ns, Precision 100PS module
name Plus, _TB (x, Y, z)
port type 
reg//input excitation port
wire//output port
Halfadder U1 (. X (x),. Y (y),. Z (z));//Instantiate the device with the Testbench port connection
initial
begin
initialize input, eg x=0;y=0;z=0;
Input excitation signal is added, exhaustive description #延迟时间 begin input excitation signal assignment; eg  #10 x =1;
End
assigns an initial value, traversing various possible
end module

Above is the template of the program

Note that the input and output in the module file in the test file, to the corresponding to the Reg and wire, there are instances when the port connection to the corresponding good

There are two types of test files, the above is the first, the direct port corresponding to the instantiation, the second and the main difference is the program at the end of the module and test files are instantiated separately