How to connect the address line between the CPU and peripherals when the flash width is 8, 16, and 32

When flash is connected to the CPU, according to different data width, such as 16-bit nor flash (A0-A19), the processor address line to (A1-A20) shift left to 1. Why is it one-digit?

From the perspective of software and CPU, an address corresponds to one byte, which is 8-bit data. This is for sure. Do not doubt this.

For a specific device, its bit width is certain. The so-called Bit Width refers to "the smallest data unit during read/write operations"-not to mention that the smallest unit is a "bit ", generally, there is no separate bitwise operation on the device. You can read, modify, and write back the entire byte, word, or double-character when modifying the bitwise.

The minimum data unit corresponding to the address line (A0-A20) of the CPU is byte, that is, 8 bits;
The minimum data unit corresponding to the address line (A0-A19) of nor flash with A Bit Width of 16 is 16 bits.
How do these two correspond?

If the peripheral width is 16, will we "specially" operate on 16 bits during program writing? No, we don't have to worry about whether the peripheral width is 8, 16, or 32 when writing a program.

If you think about it, you can actually figure it out: Since the minimum read/write unit of the CPU and peripheral nor Flash has been fixed, there must be an intermediate layer between the CPU and nor flash for processing:
This intermediate layer is called "memory controller". When the CPU needs to perform read and write operations, "memory controller" always reads/writes 16 data records each time based on the nor flash bit width.
Take the read operation as an example:
When the CPU wants to perform an 8-bit operation, it selects eight of them and returns them to the CPU;
When the CPU wants to perform a 16-bit operation, it directly returns the 16-bit data to the CPU;
When the CPU wants to perform a 32-bit operation, it initiates two reads/writes and combines the results into 32-bit and returns them to the CPU.

Now the line is: the CPU (A1-A20) to the 16-bit nor flash (A0-A19), that is, the CPU A0 is not connected-this note: whether A0 is 0 or 1, nor flash receives the same address.
When the CPU sends out 0bxxxxxxxxx0 and 0bxxxxxxxxx1 addresses, nor flash will see 0 bxxxxxxxxx, and all the data returned to "memory controller" is the same 16-bit data.
Then, the "memory controller" selects eight or eight lower bits for the CPU.

"Memory Controller" will help us do these things, for example:
1. When the software reads 8-bit data from address 0, the hardware is as follows:
① "Memory controller" issued 0b000000000000000000000 address signal, nor flash A0-A19 line signal is: 0b000000000000000000000000
② Nor flash in the Data Bus D0 ~ A 16-bit data is provided on d15, which is the 1st "minimum data unit" in nor flash"
③ "Memory controller" reads this 16-Bit Data
④ "Memory controller" returns the low 8-bit 16-bit data to the CPU, which is an 8-bit data.

2. When the software reads 8-bit data from address 1, the hardware is as follows:
① "Memory controller" issued 0b000000000000000000001 address signal, nor flash A0-A19 line signal is: 0b000000000000000000000000
② Nor flash in the Data Bus D0 ~ A 16-bit data is provided on d15, which is the 1st "minimum data unit" in nor flash"
③ "Memory controller" reads this 16-Bit Data
④ "Memory controller" returns the 16-bit high 8-bit data (Note: The previous low 8-bit data) to the CPU, which is an 8-bit data.

3. When the software reads 8-bit data from address 2, the hardware is as follows:
① "Memory controller" issued 0b00000000000000010 address signal, nor flash A0-A19 line signal is: 0b00000000000000000001
② Nor flash in the Data Bus D0 ~ A 16-bit data is provided on d15, which is the 2nd "minimum data unit" in nor flash"
③ "Memory controller" reads this 16-Bit Data
④ "Memory controller" returns the low 8-bit 16-bit data to the CPU, which is an 8-bit data.

4. When the software needs to read 8-bit data from address 3, the hardware is as follows:
① "Memory controller" issued 0b00000000000000011 address signal, nor flash A0-A19 line signal is: 0b000000000000000000000001
② Nor flash in the Data Bus D0 ~ A 16-bit data is provided on d15, which is the 2nd "minimum data unit" in nor flash"
③ "Memory controller" reads this 16-Bit Data
④ "Memory controller" returns the 16-bit high 8-bit data (note that the 3rd point is a low 8-bit data) to the CPU, which is an 8-bit data.

5. When the software reads 16-bit data from address 0 and address 1, the hardware is as follows:
① "Memory controller" issued 0b000000000000000000000 address signal, nor flash A0-A19 line signal is: 0b000000000000000000000000
② Nor flash in the Data Bus D0 ~ A 16-bit data is provided on d15, which is the 1st "minimum data unit" in nor flash"
③ "Memory controller" reads this 16-Bit Data
④ "Memory controller" returns the 16-bit data to the CPU

6. When the software reads 16-bit data on address 2 and address 3, the hardware is as follows:
① "Memory controller" issued 0b00000000000000010 address signal, nor flash A0-A19 line signal is: 0b00000000000000000001
② Nor flash in the Data Bus D0 ~ A 16-bit data is provided on d15, which is the 2nd "minimum data unit" in nor flash"
③ "Memory controller" reads this 16-Bit Data
④ "Memory controller" returns the 16-bit data to the CPU

7. When the software reads 32-bit data from addresses 0, 1, 2, and 3, the hardware is as follows:
① "Memory controller" issued 0b000000000000000000000 address signal, nor flash A0-A19 line signal is: 0b000000000000000000000000
② Nor flash in the Data Bus D0 ~ A 16-bit data is provided on d15, which is the 1st "minimum data unit" in nor flash"
③ "Memory controller" reads this 16-Bit Data

4 "memory controller" issued 0b00000000000000010 address signal, nor flash A0-A19 line signal is: 0b00000000000000000001
⑤ Nor flash in the Data Bus D0 ~ A 16-bit data is provided on d15, which is the 2nd "minimum data unit" in nor flash"
⑥ "Memory controller" reads this 16-Bit Data
7 "memory controller" combines two 16-bit data into a 32-bit data and returns it to the CPU.

From 1 ~ 7. We can see that:
① For the software, it does not know what is going on, but only the result:
Read the 8-bit data of address 0 and get an 8-bit data. Read the 8-bit data of address 1 and get the next 8-bit data.
Read the 16-bit data starting from address 0 and get a 16-bit data. Read the 16-bit data starting from address 2 and get the 16-bit data next to the other.
Read the 32-bit data starting from address 0 and get a 32-bit data. Read the 32-bit data starting from address 4 and get another 32-bit data next to it.
2) For nor flash, it only according to the A0-A19 address line, provide 16 bit data, no matter the software is 8 bit, 16 bit, or 32 bit it.
③ "Memory controller" selects and merges data between these bits.

Therefore:
When the peripheral width is 8, the CPU a0 ~ Axx and a0 ~ of peripherals ~ Axx direct connection
When the peripheral width is 16, the CPU A1 ~ Axx and a0 ~ of peripherals ~ Ayy is directly connected, indicating that no matter whether the CPU A0 is 0 or 1, the peripherals see the same address, corresponding to 16-bit data, "memory controller" to select or combine the data, then supply the CPU.
When the peripheral bit width is 32, the CPU A2 ~ Axx and a0 ~ of peripherals ~ Azz is directly connected, indicating that no matter whether the CPU a0a1 is, 10 or 11, the peripherals view the same address, corresponding to 32-bit data, "Memory Controller" selects or combines data and then provides it to the CPU.

However, not all 16-bit flash and CPU connections are staggered as above, which is related to the specific flash chip design. Therefore, you need to check its datsheet, the following describes the 29lv650 chip and Intel e29f128 chip.

 

 

Here, it seems that when the Intel nor flash is 16 bits (selected by the vpen), a0 is ignored (manual verification is required)

The following describes the differences and relationships between the system BUS address (cpu_addr), the width (bus_width), The nor flash device BUS address (device_addr), and the BIT (device_width:

1. For nor flash Devices
1. The Bit Width of nor flash devices depends on the chip manufacturer. There are two methods available: X8 and x16 (although x16 is used currently, however, the kernel still supports the X8 and x16 methods in the startup Code ); combining Multiple nor Flash files can increase the Bit Width (for example, combining two X8 nor Flash files and extending the bit width to x16 ).

2. The bus address (addressing) range of the nor flash device depends on the specific chip and Its Bit Width:

Taking Fujitsu's 29lv650 as an example:
(The capacity of 29lv650 is 8 Mbyte, with a total of 128 sector. The size of each sector is 64 kbyte)
1) if X8 is selected, each address of the device bus represents a byte storage unit, and the fixed BUS address range is 8 m (0x000000 ~ 0x7fffff );
2) If x16 is selected, each address of the device bus represents two byte storage units, and the fixed BUS address range is 4 m (0x000000 ~ 0x3fffff );

Let's take a look at Intel's e29f128:
(The capacity of e29f128 is 16 Mbyte, with a total of 128 sector. The size of each sector is 128 kbyte)
1) if X8 is selected, each address of the device bus represents a byte storage unit, and the fixed BUS address range is 16 MB (0x000000 ~ 0 xffffff );
2) If the bandwidth is x16, it is different from Fujitsu's 29lv650. In this case, the A0 foot of the device is unavailable, so you cannot access the odd address storage unit, and can only be 0, 2, 4... the bus address range is 8 m (0x000000 ~ 0xffffff's even address)

2. For the system
Taking S3C2410 as an example, the CPU bus width is 32 bits. You can use 8, 16, and 32 bits to access the nor flash device, depending on whether the device's Bit Width and usage are combined:
Note:
Buswidth = device_width * interleave:

However, in the eyes of the CPU, each address represents a 1 byte storage unit. Unlike the nor flash device, there are also byte and word.

3. After learning about the differences between the system BUS address, width, and nor flash device BUS address, and Bit Width,
Now we will discuss the connection between CPU and nor flash (for example ):

1. for Fujitsu's 29lv650
1) Select the X8 mode, CPU a0 ~ A22 is connected to a0 ~ of nor flash ~ A22
2) Select the x16 mode and the CPU A1 ~ A22 is connected to a0 ~ of nor flash ~ A21
Note:
The A1 of the CPU is connected to the A0 of nor flash, and the CPU can only access the even address. One operation of the CPU accesses a 2-byte storage unit.

2. For intel e29f128
1) Select the X8 mode, CPU a0 ~ A23 is connected to a0 ~ of nor flash ~ A23
2) x16 mode is selected, because the address line A0 is no longer valid at this time (this is different from Fujitsu's 29lv650 ),
Intel e29f128 A1 is equivalent to Fujitsu's 29lv650 A0, so the system bus A1 ~ A23 is connected to the A1 ~ of nor flash ~ A23

4. Addressing the nor flash with the CPU

1. for Fujitsu's 29lv650
1) In X8 mode, the system bus corresponds to the nor flash bus one by one and directly accesses
2) In x16 mode, nor Flash's external bus is halved, an address addressable storage unit is changed from 1 byte to 1 word (the address range of 1 sector is changed from 1 <16 to 1 <15 ), so when addressing it, we need to address the storage unit address> 1 bit
Note:
Here I am talking about the storage unit address in bytes.

Because system bus A1 is connected to nor flash A0, the fixed system BUS address is equal to nor flash BUS address <1 bit
Note:
Here I am talking about the nor flash BUS address. For X8 mode, the unit is byte, and for x16 mode, the unit is word.

2. For intel e29f128
1) In X8 mode, the system bus corresponds to the nor flash bus one by one and directly accesses
2) In x16 mode, a0 of nor flash bus is no longer used, and valid bus is A1 ~ A23, so when addressing it, we do not need to set the address of the storage unit to be accessed to> 1 bit like Fujitsu's 29lv650 (because A0 is no longer valid, if the odd address is ignored automatically, only the even address takes effect)
Similarly:
Since the A0 of nor flash bus does not work, the A1 of the system bus is connected to the A1 of nor flash, so we only need to directly give the address of the storage unit, do not compare it with <1-bit operation (however, because the device bus A0 does not work, the system can only access the storage unit of the even address, and the odd address will be ignored)

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