How to use Modelsimse to simulate IP cores-taking the PLL as an example

We have previously described how to use Modelsim se for simulation and the use of Do file simulation method, but the module to be emulated is our own Verilog module, but in the actual work, our design will often use the FPGA manufacturers to provide us with the ready-made module-IP core , these modules we can not see the source code, only know the port information of the IP core, when we want to simulate, we also have to provide these IP core information to Modelsim, and the FPGA vendors will provide us with the corresponding IP core of the compilation library files, if we include these IP cores in the design, we must before the simulation , compile these library files into the Moldelsim library. In fact, the IP core is just one of the libraries we want to add (megafunction), in addition, we need to add the LPM library (in the design if you call the LPM original, you need to add this library), as well as the original language library (primitive), the device library (we use cyclone), Of course, the same library, will also be divided into Verilog version and VHDL version. Here only to introduce the Verilog version of the relevant library file additions, VHDL version, similar methods, we just need to replace the corresponding VHDL compiled files can be. 

1.1.1. Building a simulation library

After we have compiled the IP core and other related library files into Modelsim, we will not have to add them again when we call the IP cores in the design. Let's see how to view our compiled libraries in Modelsim, open Modelsim, for example, a window named library will pop up by default, and the contents of the window will have libraries we have added, some of which are Modelsim's own library.

Now we are ready to add the relevant library files.

First step, the first in a new folder to store our compiled library file, which is named Altera_lib, we stored in the "C:\modeltech64_10.2c\" path, and then under Altera_lib New four folder LPM, ALTERA_MF, Altera_primitive, Cyclone, for example, we will create four libraries with the same name.

Second step, we build the library, and we introduce the IP core library file (ALTERA_MF) as an example. First Open Modelsim, select Menu file->new->library. Here we introduce the concept of "library", the library is actually used to hold the compilation results of a folder, he eventually and our actual hard disk on the physical space of the folder is one by one corresponding, in the fifth chapter we mentioned the Working library (work Library), stored in our own design files compiled results.

Third step, pop up the new library window, we choose the third "a new library and a logical mapping to it", that is, create a new library, and map to the corresponding path of our hard disk. The library name fills in the corresponding libraries names "ALTERA_MF", library physical name fills in our first step in the new library corresponding folder storage path. Here ALTERA_MF the corresponding folder path is "C:\MODELTECH64_10.2C\ALTERA_LIB\ALTERA_MF". then click OK.

Fourth step, in the library window of Modelsim, you can see the new ALTERA_MF library, but this time the library file is empty. Such as.

Fifth step, compile the corresponding file into the library, we need to compile the relevant IP core files into the ALTERA_MF library. Menu Bar Select Compile->compile ..., pop up the following window, first select the library libraries to be compiled, here Select our newly created library "ALTERA_MF", and then find in the Quartus installation directory, to find out what Altera provides for Altera The IP core compiles the file altera_mf.v, and the path is "Altera\13.1\quartus\eda\sim_lib". Finally click Compile, finish compiling, close. At this point, you can see that the ALTERA_MF library is no longer an empty library under the Library window.

Sixth step, repeat 2-5 steps, set up LPM, Altera_primitive, Cyclone three libraries in turn. The corresponding compilation files are 220MODEL.V (LPM), ALTERA_PRIMITIVES.V (altera_primitive), CYCLONEIV_ATOMS.V (Cyclone library, Here we have only added the Cyclone4 library file). Once added, you can see four libraries in the library, such as.

Seventh step, find the Modelsim installation path under the Modelsim.ini file, remove the read-only property of the file, and then open, add the name of the four libraries in the previous step and the path in the way, after adding to 57 rows. Close the file, and then set the read-only property. Note that the path is a backslash.

At this point, we have added Altera-related library files to Modelsim SE. Later, we'll show you how to start a simulation with a do file.

1.1.2. Introduction to the principle

Before we introduce the PLL IP core, let's start by talking about the fundamentals of the PLL. The PLL is an abbreviation for the phase-locked Loop, and the Chinese meaning is a phase-locked loop. The PLL is essentially a closed-loop feedback control system that allows the PLL output to maintain a fixed phase relationship with a reference signal. The PLL is typically composed of a phase detector, a charge amplifier (Charge Pump), a low-pass filter, a voltage-controlled oscillator (electrical), and some form of output converter. To make the PLL's output frequency a multiple of the reference clock, the divider can also be placed on the feedback path or (and) reference signal path of the PLL. The functions of the PLL are as follows:

First of all to understand what is a voltage-controlled oscillator (VCO), the voltage-controlled oscillator is actually a: frequency-to-voltage converter. When the voltage of the VCO input changes, the frequency of the corresponding output also changes. The PLL works by returning the frequency of the VCO output over the divider to the input, separating the divider signal from the original input signal, the phase detector output being converted to a voltage by a voltage amplifier and a low-pass filter, and adjusting the VCO's input voltage, thus adjusting the VCO's output frequency and then looping , and eventually the output frequency is locked.

1.1.3. Establishing an IP core

First step: the new Pll_test project according to the method of 2.4.2, here we will not repeat, after the new project. Select the menu bar Tools->megawizard plug-in Manager. One of the Megawizard is the Quartus IP Core Setup Wizard tool, which we use to build the IP cores we need.

Second step: Pop up the following dialog box, select "Create a new custom megafunction variation", creating a newer IP core. Click Next.

Third step: Pop Up the following dialog box, first introduce the IP core Search bar, we can quickly find the location of the required IP core through this place, we enter the PLL, we can quickly find the PLL IP core, ALTPLL, such as. Here to generate the IP core file, we chose to Verilog.

Fourth step: Click on the IP Core storage path, select the storage path, for example, we store to SRC/IP folder, here must be in the file name to fill in the IP check should be the name of the output file, here we define as PLL.V. Then click "Open" to go back to the Third step window and continue next.

Fifth step: The configuration window of the PLL IP core will be ejected at this time. First set the device speed level, we use the device speed level of 8. The smaller the speed level, the faster the corresponding FPGA speed. Then set the PLL input frequency, here we set to 50MHz, other default. Click Next.

Sixth step: The following dialog box appears, keeping the default option, which is to create an asynchronous input signal, note that this reset signal is active high, create a PLL lock locked signal. Continue next.

Seventh step: Always click Next, the middle process configuration remains the default until the tab is Output CLOCKS->CLK C0, which means that the PLL outputs clock is configured, and the "Use this clock" option of the CLK C0 is selected by default. Select "Enter Output clock frequency" and set the clock frequency for the desired output under "requested Settings", where CLK C0 is set to 100MHz. Then click Next.

Eighth step: Pop the same window, here we need to manually select "Use this Clock", the same method to create a CLK C1 40MHz clock, CLK C2 for 10MHz clock. C3, C4 not enabled.

Nineth Step: Continue next, the middle process remains the default, until the summary option, you can choose the actual output of the file, here pll.v is necessary, this file is the future of our simulation when the IP of the compiled file. Second, we select the Pll_inst file, which is the PLL's sample file, and we can copy the PLL's instantiated results directly from the file into the appropriate application logic. Finally click Finish.

Tenth step: Call the IP core, first create a new top-level file, PLL_TEST.V file, refer to the SRC folder under the source file. Locate the SRC/IP path under the PLL_INST.V file, open. Copy the example example into the top-level file. Adjusts the PLL's instantiated port based on the top-level IO information. The code is as follows.

1. Module pll_test

2. (

3. input I_CLK,// module Input Clock , 50MHz

4. input i_rst_n,// reset signal, low active

5. output O_clk_100mhz, //100mhz clock out

6. output O_clk_10mhz, //40mhz clock out

7. output O_clk_40mhz, //10mhz clock out

8. output o_led_done //led light, clock LOCK

9.);

Wire W_pll_lock ;

One. PLL Pll_inst (

Areset (!i_rst_n),

Inclk0 (I_CLK),

C0 (O_clk_100mhz),

C1. (O_clk_10mhz),

C2.: (O_clk_40mhz),

Locked.: (W_pll_lock)

18.);

assign O_led_done =!w_pll_lock;

Endmodule .

At this point, we have completed the entire IP core establishment and invocation process, the next section we introduce the IP core simulation.

1.1.4. Starting the simulation

The simulation library has been set up in the 2.10.1 section, and when you simulate any IP cores later, you do not have to repeat the operation of section 2.10.1. Now, we can simply modify the contents of the Do file to start the simulation directly from the Do file. The following is the contents of the Sim.do file in this section.

vlib Work

Vmap Work

vlog . /sim/*.v

vlog . /src/*.v

vlog . /src/ip/pll.v

Vsim- T PS -novopt-l lpm-l altera_mf-l cyclone-l altera_primitive work.tb_pll_test

As you can see, the vsim instruction of the sim.do file in this section has several options-----lpm-l altera_mf-l cyclone-l altera_primitive, than the Vsim directive we experimented with earlier. These options actually add the 4 libraries we created in section 2.10.1 to our simulation, and-L represents the library, followed by the name of the corresponding library. Second-T represents the simulation time unit, where we need to adjust the time unit of the simulation to PS, otherwise the PLL simulation does not have waveforms. It is important to note that when compiling the IP-core makefile, only the PLL.V can be compiled, and the PLL_INST.V file we generated earlier does not compile. Otherwise you will get an error.

After modifying the above items, we then double-click on the Modelsim_run.bat file, we can start the simulation and see our true waveform.

How to use Modelsimse to simulate IP cores-taking the PLL as an example