I2C Bus Simple Summary

1. Overview

I2C is a two-wire interface that I2C only two bidirectional lines, one serial Data line (SDA), and the other serial Clock (SCL).

SCL: The data is entered into each EEPROM device by the ascent, and the output data is dropped along the drive EEPROM device. (Edge Trigger)

SDA: Two-way door, with any number of other OD and OC gate into "line and" relationship.

2. Output level

The SDA and SCL PIN circuit structures within each I2C bus device are the same, and the output of the pins is connected with the input buffer. wherein the output is an open field effect tube of the drain electrode, and the input buffer is a high input impedance of the same direction device, which has two characteristics:

1), due to SDA, SCL open circuit structure (OD), so they must be connected with the pull resistance, the resistance of the size is often 1.8K, 4.7K, 10K, but 1.8K when the best performance; When the bus is idle, two lines are high level. The low level of the output of any device connected to the bus will make the signal of the bus lower, that is, the SDA of each device and the SCL are line "and" relationship.

2, the pin in the output signal at the same time also the pin on the level of detection, detection and just output consistent, for "clock synchronization" and "bus arbitration" to provide a hardware base.

3. Main equipment and from equipment

All peripheral devices in the system have a 7-bit "from the device specific address code", of which the high 4-bit device type, developed by the manufacturer, the low 3-bit for the device PIN definition address, defined by the user. The main control device establishes the mechanism of the multi-machine communication through the address code, so the I2C bus eliminates the chip selection of peripheral devices, so no matter how many devices are hung on the bus, the system is still a simple second-line structure. Terminal mount on the bus, there is the main end and from the end of the point, the main end must be a logic module with the CPU, on the same bus at the same time to enable a master, can have multiple from the end of the number of address space and the maximum capacity of the bus 400pF limit.

• The main end is mainly used to drive the SCL line;

• Respond to the main device from the device

Both can transmit data, but the transmission is not initiated from the device and the transmission is controlled by the master device.

4. Rate

Normal Mode: 100kHz

Quick mode: 400kHz

High Speed mode: 3.4MHz

There is no need to use a high speed SCL to keep the SCL at 100k or below;

I. Agreement

1. Idle state

The SDA of the I2C bus and the SCL two signal lines are at the same time at high power, which is defined as the idle state of the bus. At this point, the output pole FET of each device is in the cut-off state, that is, the release of the bus, by the two signal lines of their respective pull resistance to the level of higher.

2. Definition of starting bit and stop bit:

• Starting signal: When the SCL is high, the SDA jumps from high to low, and the starting signal is a level-hopping timing signal, not a level signal.

• Stop signal: When the SCL is high, the SDA jumps from low to high, and the stop signal is a level-hopping timing signal, not a level signal.

Each time the transmitter sends a byte, it releases the data line between the Pulse 9 and the receiver responds with an answer signal. The response signal for the low electricity peacetime, defined as a valid answer bit (ACK short answer bit), indicating that the receiver has successfully received the byte-change, the response signal for high power peacetime, defined as a NACK bit, generally means that the receiver received the byte did not succeed. The requirement for a feedback effective response bit ACK is that the receiver pulls the SDA line down during the low level prior to the 9th constant pulse and ensures a stable low level during the high level of the clock. If the receiver is the host, after it receives the last byte, it sends a NACK signal to notify the accused transmitter to end the data sending and release the SDA line so that the master receiver sends a stop signal p.

The following diagram of the Logical Analyzer sample results: When the bus is released, if there is no response signal, SDA should continue to be high level, but as shown in the blue dotted section of the figure, it is pulled low to low level, proof received the response signal.

Here are two messages for me:

1. The receiver pulls down the SDA during the low level before the SCL rises along the arrival;

2), the response signal has been maintained until the SCL drop along the end, as the red logo pointed out earlier.

4, the validity of the data:

I2C bus for data transmission, always signal for high level, data line data must remain stable, only on the clock line signal for the low level, the data line on the high level or low level state to allow changes.

Self-understanding: although only required to maintain stability during the high level, but there is an advance, that is, data in the SCL rise along the arrival of the need to be prepared, because the previous article has been pointed out that the data is on the rise of the SCL into the device.

5, the data transmission:

Each bit of data transmitted on the I2C bus has a clock pulse corresponding to (or synchronous control), that is, in conjunction with the SCL serial clock, sequentially transmitting each bit of data on the SDA. The transmission of data bits is an edge trigger.

Ii. process of work

All traffic on the bus is caused by the main controller, and in a single communication, the main controller and the controller always play two different roles.

1. The main device sends data from the device

The primary device sends the start bit, which notifies all devices on the bus that the transmission begins, and then the host sends the device address, and the slave that matches the address will continue the transmission, while the other slave will ignore the next transmission and wait for the next transmission to begin. After the primary device is addressed to the device, it sends the internal register address of the device that it will read or write from, and then sends the data. Send stop bit when data is sent.

The write process is as follows:

Send Start bit

• Send the address from the device and read/write select bits, release the bus, wait until the EEPROM to pull down the bus to answer; If the EEPROM received success, then answer, if there is no handshake success or send the data error when the EEPROM does not produce a response, this request to resend or terminate.

• Send the internal register address you want to write, and the EEPROM responds to it;

• Send data

· When the EEPROM receives the stop signal, it enters into an internal writing cycle, requiring 10ms, which will not be answered by the EEPROM during this period; (This can result in a delay between two writes, which can cause failure)

Description

The ① main controller establishes a communication relationship with the corresponding controller by sending the address code. While the other controller attached to the bus also receives the address code, but because it does not conform to its own address, it exits the communication with the main controller in advance;

2, the main controller read the process of data:

The process of reading is more complex, before slave read out the data, you must first tell it which internal registers need to be read, so you must write to them first:

• Send Start bit

• Send slave address +write bit set

• Send Internal Register address

• Resend start bit, i.e. restart

• Resend slave address +read bit set

• Read data

When the host sink receives the last byte, it does not emit an ACK signal, so the SDA line is released from the machine transmitter to allow the host to emit a P signal to end the transmission.

• Send Stop bit

In order to deepen the understanding of the I2C bus, the C language is used to simulate the IIC bus, as shown in the sequence diagram of write operation

The procedure is as follows:

#include <reg51.h> #define UCHAR unsigned char #define UINT unsigned int #define WERITE_ADD 0xa0 #define READ_ADD 0xa
1 Uchar A;
Sbit Sda=p20;
Sbit scl=p21; void Somenop (); Short delay void init ();
initialize void check_ack (void);
void I2cstart (void);
void I2cstop (void);
void Write_byte (Uchar dat);//write Byte void delay (UINT z);
Uchar Read_byte ()//read byte void write (Uchar addr,uchar dat);//Specify Address write Uchar read (Uchar addr);
	Bit flag;//answer flag bit void main () {int ();
Write_add (5,0XAA)//To address 5 write 0XAA delay (10),//Delay 10ms P1=read_add (5);//Read the value of Address 5 while (1);
	} void Delay () {;} void Start ()/Start signal SCL at high level, SDA a descent indicates the start signal {SDA=1;//S release SDA bus delay ();
	scl=1;
	Delay ();
	sda=0;
Delay ();
	void Stop ()//stop signal, SCL at high level, SDA a rising edge indicates stop signal {sda=0;
	Delay ();
	scl=1;
	Delay ();
	Sda=1;
Delay ();
	} void Respons ()//answer, SCL at high level, SDA is pulled from device to low level to express reply {Uchar I;
	scl=1;
	Delay ();
	Wait at most 250 CPU clock cycles while ((sda==1) && (i<250)) i++;
	scl=0;
Delay ();
} void Init ()//bus initialization, which pulls the bus up--before releasing the bus to send the boot signal, initialize the bus first, that is, the bus is idle before it detects the bus to start sending the start signal {	Sda=1;
	Delay ();
	scl=1;
Delay ();
	} void Write_byte (Uchar date)/write a byte {Uchar i,temp;
	Temp=date;
		for (i=0;i<8;i++) {temp=temp<<1;	
		scl=0;//to lower the SCL, because only when the clock signal is low level to the high and low level in the data line state to allow the change, and at this time and the previous cycle of the scl=1 together to form a rise along the delay ();
		Sda=cy;
		Delay ();
	scl=1;//to pull high SCL, at this time the data on the SDA stable delay ();
	scl=0;//lower the SCL to prepare for the next data transfer delay ();
sda=1;//releases the SDA bus, then pulls down the SDA as the response signal delay () from the device control, such as after receiving the data from the device, when the SCL is high;
	Uchar Read_byte ()//read one byte {Uchar i,k;
	scl=0;
	Delay ();
	Sda=1;
	Delay ();
		for (i=0;i<8;i++) {scl=1;//rise along, the IIC device puts the data on the SDA line and the data is stable during the high level, and can receive delay ();
		k= (k<<1) |SDA;
	scl=0;//Low SCL delay ();
} return k;
	void Write_add (Uchar address,uchar data)/write one byte {start ();/start Write_byte (0xa0);
	Respons ()//waiting for the response from the device Write_byte (address)//Send out the chip respons ();
	Write_byte (data);
	Respons ();
Stop ();
	Uchar Read_add (Uchar address)/read a byte {UCHAR data;
	Start ();
	Write_byte (0xa0)//Send from the device address, write Operation Respons (),//wait from the device response Write_byte (address);
	Start (); Write_bYte (0XA1)//Send from device address read operation Respons ();
	Data=read_byte ();//Get Data Stop ();
	
return data;
 }