Important design ideas of FPGA

FPGA Important Design Ideas

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1. speed and area swap principles. in the area of speed can achieve a very high data throughput rate, in fact , the string / and conversion, is an area of the idea of Speed change

2. Ping-pong operation.

3. The idea of string/and conversion.

One of the important techniques for high speed data processing. Here, let me give you an example of a multiphase filter extraction:

After extraction, two-way data is processed at a two-frequency rate

4. Pipeline design ( very prominent in fir filter, one clock output one data)

Pipeline design can improve the system frequency to some extent. The premise is that the design can be divided into several steps to deal with, and the whole process of data processing is one-way, that is, no feedback or inverse operation, the output of the previous step is the input of the next step ...

5. logical replication and module reuse.

Module multiplexing is widely used in saving logical resources (for example)

Contrast, not much to say, a case of victory thousand words!

As for the logical copy, later on, we haven't met yet. Copy the concept first: logical replication is an optimization method to improve the timing condition by increasing the area, and its most important application is to adjust the fan-out of the signal. In other words, the fan-out is very large, so in order to increase the driving capacity of this signal, it is necessary to insert a lot of Buffer, which increases the signal's path delay to a certain extent. In this case, it is possible to assign a value to generate the logic of this signal, with a multi-channel same-phase signal to drive the subsequent circuit, is the average to each Luther fan out of the lower, so that no need to insert Buffer to meet the demand for increased drive capacity, thereby saving the signal path delay.

Anyway. Module multiplexing saves area, sacrifices speed, and logical replication is reversed.

6. Modular Design

Is the top-down design method. Not discussed, very simple has very rare things.

7. Clock Design tips

try to avoid using FPGA internal logic produces a clock because it can easily cause problems with functionality or timing. The clock generated by the internal combinational logic is prone to burr, which affects the function realization of the design, and the inherent delay of the combinational logic can lead to the timing problem.

If the output produced by the internal combinational logic is used as a clock signal or an asynchronous reset signal, glitches may inevitably occur. If the signal is in the process of transformation, then it will violate the settling time and hold time requirements, thus affecting the output status of the subsequent circuit, and even the entire system failed to run.

If you want to reduce burr, it is best to use the clock to hit. Achieve the effect of synchronous processing.

In the design of the need to use the frequency divider clock, should try to use the Enable clock, so that the frequency division signal as the enable signal to use.

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Bruce Lone

. years 4 Month - Day Sunday

Important design ideas of FPGA