In-depth analysis of I/O Constraints

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Edn blog highlightsArticleAuthor: ilove314

Question: I have been exploring Timing Analysis for a long time. I have read a lot of data and reviewed the comparison and summary. Then I think about it. At last, I feel a little enlightened, but I still don't have enough things to fully understand. I also like to share my thoughts with you, I hope that you can put forward some ideas and make progress in the continuous discussion and summarization.

Quartus II Ti The integrated design constraints of mequest Timing Analyzer support the design pin constraints. These constraints allow Quartus II timequest Timing Analyzer to perform system static timing analysis, including not only FPGA timing, but also timing of any external device and board-level timing parameters.

Input and Output Delay

Specify any external device or board-level parameters using input/output latency constraints. When you apply these constraints, Quartus II timequest Timing Analyzer performs static timing analysis throughout the system.

Set input delay

The set_input_delay constraint specifies the data arrival time of a pin (device I/O) on a given clock. Figure 6-26 shows an input delay path.

Use the set_input_delay command to specify the input delay of the design pin. Example 6-18 shows the set_input_delay command and options.

Table 6-14. set_input_delay Command Options

 

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If you only specify a-Max or-min value for the input delay value, a warning message is displayed. At this time, the default value of the unspecified input minimum latency value or maximum latency value is the same as that of the other party. Similarly, if you only specify a-rise or-fall value for the latency value, a warning will also appear. The default latency value is also set in the same way as the maximum and minimum latency values of the input.

The maximum value is used to establish a time detection, while the minimum value is used to maintain time detection.

By default, the input delay (min/max, rise/fall) can be set to a combination of clock,-clock_fall, and-reference_pin. Specify the input delay value for an identical pin. If you do not want to remove these different clock,-clock_fall, or-reference_pin, you must specify the-add_delay option. When you specify the-add_delay option, the worst case value will be used.

-Rise and-fall options are mutually exclusive, and-min and-Max options are also mutually exclusive.

Set output delay

The set_output_delay command specifies the time required for data on a given clock-related pin (device pin. Use the set_output_delay command to specify the output delay constraint of the design pin. Figure 6-27 shows an output delay path.

The Command Options are similar to set_input_delay, Which is skipped here.

Other instructions are similar to set_input_delay, Which is skipped here.

The following describes the key concepts of the maximum (minimum) latency of input (output) in the I/O constraints.

 

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As you can see, the Maximum/minimum latency of input is set for some features of the external device. The so-called maximum input latency (Here we assume that the system is in an ideal state, that is, the external device and FPGA share a clock source without considering clock skew, that is to say, the clock is synchronized to the external device and the FPGA lock edge), that is, the maximum TCO latency of data transmitted from the clock along the external device + the PCB cabling latency; and the minimum input latency, it is the minimum TCO latency of data passing through external devices + the latency of PCB cabling. What is the relationship between this time and the internal build-up time of FPGA?

Like general timing analysis, the data input from external devices to FPGA must also meet the requirements for establishing the retention time. The most common understanding of the maximum input latency is that the data of external devices reaches the FPGA port at the latest time, the latest time may not be too late. You must consider the time Tsu was created when FPGA locks the data. If the data arrives late at the Tsu time before the clock lock, the clock will not be able to lock the data. Therefore, the maximum latency of the input must meet the first condition: Tsu + input maximum latency <clock cycle tclk (the first formula ).

Similarly, the shortest time for this data to reach FPGA is called the minimum input latency. This shortest time cannot be too fast. If the data in the clock transmitting along the external device passes the TCO and PCB cabling of the external device in a very short time, when the FPGA port is reached, it is assumed that the FPGA is out of the retention time th of the data transferred from an external device, the new data will inevitably destroy the retention time of the previous data, which will also cause time series violations. In this case, the minimum latency of the input cannot be too small, and certain conditions must be met: th <The minimum latency of the input (that is, the second formula ).

 

After so much discussion, I believe you should understand it. I will not talk about the concept of PCB clock skew, you can understand that the source clock has a certain deviation when the signal transmitted in the PCB wiring reaches the corresponding lock port time, so this deviation is the PCB clock skew, so why is this value subtracted rather than added? You can understand that the PCB clock skew value = the time when the clock source reaches the FPGA port-the time when the clock source reaches the external device port, and then ~~ Digest it slowly!

We recommend that you refer to the explanation of input_delay for synchronous timing constraints in the article of wind330 Boyou:

Http://blog.ednchina.com/wind330/194897/message.aspx

The concept of Maximum/minimum latency of input is quite clear, and the concept of Maximum/minimum latency of output is similar. The first formula is actually the same as the first formula for the maximum/minimum latency of the input, but it is not hard to understand that it swaps the position of the subtraction.

However, for the second formula, I personally understand that it is not the same as what was proposed in the official guide of Altera. My understanding is as follows: the fastest time for FPGA output data to reach the external device input pin = TCO + PCB wiring latency, and according to the analysis of the second formula in the input Maximum/minimum latency, the th of the external device should be smaller than the above value, that is, the th of the external device <TCO + PCB wiring latency (do not discuss PCB clock skew first), so the TCO> TH-PCB wiring latency is correct, instead of TCO> output minimum latency = TH + PCB wiring latency.

The above is my understanding of this formula. Maybe the analysis is incorrect. I hope you can give me some advice!