In-depth introduction to the cp0 coprocessor of MIPS three MIPS

From: http://www.kernelchina.org /? Q = node/273

In the mips architecture, a maximum of four co-processors are supported ). Cp0 must be implemented in the architecture. It controls the CPU. MMU, exception handling, multiplication and division, and other functions depend on the cp0 of the coprocessor. It is one of the essence of MIPS and opens the door to the MIPs privileged level mode.
Cp0 of MIPS contains 32 registers. For more information about them, refer to the official MIPS documents mips32 (r) architecture for programmers Volume III: Chapter 7 and chapter 8 of the mips32 (r) Privileged resource architecture. This article only discusses some common registers.
Register 0: Index, used as the MMU index. We will discuss MMU and TLB in the future.
Register 2 and entrylo0 are used to access 32-bit low addresses on the even page of TLB entry. Same as above, which is explained in the relevant chapters of MMU and TLB.
Register 3, entrylo1, which is used to access 32-bit low addresses on the odd page of TLB entry.
Register 4 and context are used to accelerate the handling of TLB Miss exceptions.
Register 5, pagemask, used to allocate variable memory pages in MMU.
Register 8, badvaddr. When the system detects the TLB miss or address error exceptions, the virtual address with the error will be stored in the register. This register is very important for locating bugs that cause exceptions.
Register 9, Count. This register is introduced by the MIPs system after r4000. It is a counter with a counter frequency of 1/2 of the system clock speed. Bcm1125/1250, rmi xlr series, and octeon's cavium processors all support this register. For the operating system, you can obtain the tick time base by reading the value of this register. In the system performance test, this register can also be used for hitting counting.
Register 10, entryhi, which is the same as entrylo0/1 and used in MMU. It will be detailed later.
Register 11, compare, used with count. When the Compare and count values are equal, a hardware interrupt (Hardware Interrupt) is triggered, and the cause register's ip7 bit is always used.
Register 12, status, used to control the processor status.
Register 13, cause, which reflects the cause of a processor exception.
Register 14, EPC, the address of the command being executed by the system when an exception occurs in this register.
Register 15, PRID. This register is read-only and identifies the version information of the processor. Writing to it is meaningless.
Register 18/19, watchlo/watchhi, which is used to set a hardware data breakpoint (hardware data breakpoint ). Once this breakpoint is set, an exception occurs when the CPU accesses this address. This function is widely used for debugging and locating memory write errors.
Register 28/29, taglo, and Taghi are used for Cache Management.

Below, we will explain several registers commonly used in cp0: badvaddr, count/compare, status/cause, EPC, watchlo/watchhi.

Badvaddr: Incorrect virtual address. In fact, this register can be used only when TLB miss and Ade (address error) Exceptions occur. The virtual address with an error will be placed in this register.
Generally, when TLB is set, a block near the 0 address is usually set to a non- ing area. In this way, the system will throw a TLB Miss exception once a blank pointer (0 address) is accidentally accessed during programming, or a certain offset is added to the NULL pointer. In this case, the wrong address is recorded in the badvaddr register. Generally, this address is very close to 0. Often, through the badvaddr value in the register, and the analysis of the relevant data structure, you can find the corresponding statement.
In addition, for Ade exceptions, the exception address will also be saved in badvaddr. Generally, the operating system takes over the address and reads/writes the data at the address twice without the core dump. However, if the address is neither an alignment address nor a TLB Miss address, the system will throw a core dump. Normally, the operating system should correctly handle this exception. if the address is not mapped in TLB in exception handler, the Ade exception should be thrown instead of TLB miss.

Count/compare: These two registers are a pair of happy friends in cp0. Count is a counter. Every two system clock cycles increase by 1. When its value is equal to compare, a hardware interruption (Hardware Interrupt) occurs ). This feature is often used to provide a reliable tick time for the operating system.

Status: This register identifies the processor status. Among them, the eight IM (Interrupt Mask) bits for interrupt control and the RE (reverse endianess) bits for setting the processor size. 8 im BITs, which can control 8 hardware interrupt sources respectively. They will be explained in detail when talking about 'hardware Internet. The re bit is very interesting. setting this bit allows the CPU to switch between the big endian and little endian. By default, the MIPs processor is a large-end, the same as the network sequence. However, to run a Windows NT-like server operating system on MIPS, setting this bit allows the processor to work in little endian mode.
Cause: When a processor exception occurs, this register identifies the cause of the exception. Among them, the most important is the excetion code bit of 5 bits from bit2 to bit6. They identify the cause of the exception. The specific value indicates the exception type, as shown below:
0: interrupt, interrupted;
1: TLB modified, trying to modify the memory address mapped to read-only in TLB;
2: TLB Miss load, trying to read a virtual address that is not reflected in the physical address in TLB;
3: TLB misses the store and tries to store data to a virtual address not mapped to a physical address in TLB;
4: Address error load, trying to read information from a non-alignment address;
5: Address error store, which attempts to write information to a non-alignment address;
6: instruction bus error, which is generally a command cache error;
7: Data Bus error, which is generally a data cache error;
8: syscall, which is generated by the syscall command. In the operating system, a common method is to switch from user to kernel. It is similar to the "Call door" of ia32;
9: break point, which is generated by the break command. The most common BP command is generated by the compiler. A break point command is inserted during Division operations to throw error messages when division is 0. Therefore, if a break point exception is found when the problem is located and Its Exception Code is code 07, the division of 0 should be considered;
10: Ri, reserved command. This exception occurs when the CPU executes an unspecified command;
11: Co-processor unavilible. The coprocessor is unavailable. This exception is caused by an attempt to operate non-existing coprocessor. In particular, executing this command on a processor without a floating-point coprocessor can cause this exception. The operating system then calls the Lib library that simulates floating points to implement floating point operations of the software;
12: overflow, Arithmetic overflow. Only signed operations will cause this exception;
13: trap. This exception comes from the trap command. Similar to the syscall command, the trap command also causes an exception, but the trap command can be attached with some conditions, which can be used for debugging programs.
14: vcei, indicating that the Virtual Address consistency in the instruction cache is incorrect. (I don't know what's going on. I still need to be supplemented by experts)
15: Float Point exception, floating point exception;
16: Co-Processor 2 exception, coprocessor 2 exception;
17 ~ 22. For future extension;
23: Watch, memory breakpoint exception. It works when two registers watchlo/watchhi are set. When the virtual address of load/store matches with watchlo/watchhi, this exception occurs./* this local classic book "see MIPS run" makes a mistake, write the virtual address as a physical address */
24 ~ 30. reserved for future extension;

EPC: this register is used to save the instruction address when an exception occurs. From this point, you can find the command for the exception, and then combine the badvaddr, SP, RA and other registers to export the program call relationship during the exception, so as to locate the root cause of the problem. Once the EPC content is lost when an exception occurs, locating the exception is very difficult.
Watchlo/watchhi: This register can be used to set "memory hardware breakpoint", that is, to monitor the memory at a specified point. An exception occurs when the accessed memory address is the same as the address in the two registers. Some MIPS processors have made some modifications to the functions of these two registers to adapt to some 64-bit extended functions, which is different from the definition of the mips architecture, such as RMI multi-core processors.

For access from the coprocessor cp0, special commands are required. These commands are "privileged-level commands" and can be executed only in the kernel mode. In user mode, an exception occurs ).
The main operations on cp0 are as follows:
Mfc0 RT, RD transfers the RD register content in cp0 to the RT General Register;
Mtc0 RT, RD transfers the content in the general RT register to the RD register in cp0;
Mfhi/mflo RT transfers the content of the cp0 hi/LO register to the RT General Register;
Mthi/mtlo RT transmits the RT General Register content to the HI/LO register of cp0;
After the mips architecture evolved to the 64-bit architecture of mips iv, two new commands dmfc0 and dmtc0 were added to read/write a 64bit data to the cp0 register.

As mentioned above, the mips architecture is a five-level pipeline architecture with no mutual lock and high flow. This means that if the previous command has not been executed, the next instruction may have entered the instruction/decoding stage. In this way, the so-called cp0 risk (cp0 hazard) phenomenon may occur. To put it simply, the execution speed of the MFC and MTC commands is relatively slow. Therefore, when the next command is executed, it is possible that the value of the cp0 Register has not been finally transmitted to the specified target general register. At this time, if you read this general-purpose register, it is possible that the correct value is not obtained. This is the so-called cp0 adventure.
To avoid the risk of cp0, we need to add an instruction irrelevant to the target general register of the previous instruction after the cp0 operation instruction during programming, that is, the delay slot ). If you are not sensitive to performance, you can use a NOP null Operation Command to fill the delay slot.
For example, content that often appears in exception handler:

....
Mfc0 K0, $ cause
NOP/* mfc0 command execution speed is slow, add an empty operation in the delay slot */
MoV T0, K0/* place the content of the cause register to t0 for next operation */