Information Security System Design Foundation Sixth Week study summary

Fourth Chapter processor Architecture4.1 Y86 instruction set architecture

Defines an instruction set architecture, such as Y86, that includes defining various state elements, instruction sets, and their encodings, a set of specifications, and exception event handling.

1 visible state of the programmer

1 Programmer-visible states: Each instruction in Y86 reads or modifies portions of the processor state. The "programmer" here can be either the person who writes the program with the assembler code or the compiler that produces the machine code.

The processor state of the Y86 is similar to IA32. There are 8 program registers:%eax,%ecx,%edx,%ebx,%esi,%esp and%EBP. Each program register of the processor stores one word.

2 memory, conceptually a large byte array, holds the program and data. The Y86 program uses a virtual address to refer to the memory location. Hardware and operating system software are combined to translate virtual addresses into actual or physical addresses, indicating that the data is actually stored in the storage area.

2 Y86 means

The Y86 instruction set is basically a subset of the IA32 instruction set. It includes only four-byte integer operations, less addressing, and fewer operations. Because there are only four bytes of data, there is no ambiguity in what is called a "word".

On the left is the assembly code representation of the instruction, and the right is the byte encoding. The sink encoding format is similar to the IA32 att format.

1. In the MOVL directive, the first letter of the instruction name indicates the source type. The second letter of the instruction indicates the purpose type. Immediate count (i), register (R), memory (m). Memory references in two memory transfer instructions are simple base and offset forms. In address calculation, the scaling of the second and any register values is not supported. It is not allowed to transfer directly from one memory address to another, nor is it allowed to transfer the immediate number to memory.

The 2.addl,subl,andl,xorl is a four integer operation instruction that only allows operation of the register data in the Y86 (also allowing operation of the memory data in the IA32), which sets the condition code ZF, SF, of.

3.JMP,JLE,JL,JE,JNE,JGE,JG is a seven jump instruction that selects branches based on the type of branch instruction and the setting of the condition code.

The 4.CMOVLE,CMOVL,CMOVE,CMOVNE,CMOVGE,CMOVG is a six conditional delivery instruction that has the same format as the Register-register transfer directive, but updates the value of the destination register only if the condition code satisfies the required constraint.

The 5.call instruction returns the address to the stack and then jumps to the destination address. The RET instruction is returned from such a procedure call.

The 6.PUSHL and POPL instructions are implemented into the stack and out of the stack.

The execution of the 7.halt instruction stop instruction (instruction hlt in IA32). The application in IA32 does not allow this instruction because it causes the entire system to pause. For Y86, executing the halt instruction causes the processor to stop and set the status code to HLT.

3 instruction encoding

1. Each instruction requires 1~6 of bytes, depending on which fields are required.

The register number in 2.86 is the same as in IA32. Program registers exist in a register file in the CPU, this register file is
is a small, random-access memory with the Register ID as the address. In the instruction code and in our hardware design, it is indicated by the ID value 0xF when it is necessary to indicate that no registers should be accessed.

3. Some instructions have only one byte long, and some require an operand to encode it longer. First, there may be additional register designator bytes , specifying one or two registers.

4. The Assembly code representation of the instruction shows that, depending on the instruction type, the instruction can specify a register for the data source and destination, or a base address register for addressing computation. Without a register operand, such as branch instruction and call instruction, there is no register designator byte. Those instructions that require only one register operand indicate the other register as subscript character to OXF. This kind of convention is very useful in our processor implementations.

5. Some instructions require an additional 4-byte constant number.

4 Y86 Anomalies

For Y86, when these anomalies are encountered, we simply let the processor out of the execution instructions.

In a more complete design, the processor typically invokes an exception handler, which is specified to handle some type of exception encountered.

5 Y86 Program

The main difference between the Y86 code and the IA32 code is that it may require more than one instruction to perform the functions performed by a IA32 instruction.

The Y86 does not have a scalable addressing mode.

The command indicates where the code or data should be placed, and how to align it. This procedure details the prevention of stack, initialization of data, initialization of program and end of program.

With "." The first word is the assembly command, which tells the assembler to adjust the address so that it can generate code or insert some data there. command. Pos0 tells the compiler to generate code starting at address 0. This address is the starting point for all Y86 programs.

The only tool for creating Y86 code is the assembler.

The purpose of the instruction set simulator Yis is to simulate the execution of Y86 machine code programs without attempting to emulate the behavior of any specific processor implementation. This form of simulation helps to debug the program before the actual hardware is available, and also helps to check the results of simulated hardware or running the program on the hardware.

Details of some Y86 directives

Most Y86 directives modify the state of a program in a straightforward way.

6 details of some Y86

• Most Y86 directives modify the state of the program in a straightforward way, so it is not difficult to define the results that each instruction wants to achieve. However, two special instruction combinations require special attention. The PUSHL instruction will reduce the stack pointer by 4 and write a register value to the memory. Therefore, when the PUSHL%esp instruction is executed, the behavior of the processor is indeterminate, because the register to be placed on the stack is modified by the same instruction.
• There are usually two Conventions: 1) Press the original value of the%ESP, 2) and press the value of the%esp minus 4.

4.2 Logic Design and hardware control Language HCL

1 Logic Gates

1. output generated by logic gates: A Boolean function equal to their input bit value.

2. the corresponding HCL expression:

and use && to denote OR to use | | represents Not used ! represents

3. Note: The logic gate operates only on the number of individual bits, not the entire word.

The logic gate is always active, and the input change output quickly follows the change.

Refer to the C language operator (2.1.9 section)

2 combinational circuits and HCL boolean expressions

1. limitations of building compute blocks (called combinational circuits)

Outputs of 12 or more logic gates cannot be connected together 2 must be no ring

2. the difference between logical expressions in combinational logic Circuits and C language

1 The output of the combined circuit will continue to respond to input changes, and theC language expression is evaluated only when it is encountered during execution

2 The logic gates operate only on 0 and 1 ,the parameters in the C language expression can be any integer, and0 is FALSE, not 0 is TRUE

3C 's logical expression has a property that they may only be partially evaluated

3-character combination circuit and HCl integer expression

1. a Few notes on the HCL all Word-level signals in the HCL are declared as int;

In a stooped class circuit, a line representing each bit of the word with a medium-coarse thread, with dashed lines representing the result of the Boolean signal

In the HCL , it means that the default (that is, all conditions are not selected) is typically 1

2. description of the condition expression of the multiplexed function

[

Select_1:expr_1

Select_2:expr_2

.......

Select_k:expr_k

]

Logically, these selection expressions are evaluated sequentially.

4 Collection Relationships

The general format for judging set relationships is: iexpr in {iexpr1,iexpr2,..., IEXPRK}

Note: Tested values iexpr and matched values iexprk are integer expressions

5 Memory and Clock

Sequential circuit Two types of memory devices:

(1) clock Register (register): stores a single bit or word. Clock signal control register load input value

(2) random access Storage (for short): store multiple words, use the address to choose which word to read or write

4.3 Y86 sequence Implementation 1 will process the organization into stages

Here is a brief description of the phases and the actions performed during each phase:

Fetch refers to the value of the program counter (PC), which reads the instruction bytes from the memory during the reference stage.

Decoding: The decoding phase reads a maximum of two operands from the register file, resulting in Val a/val B.

Execution: The arithmetic/logic unit performs an explicit operation (according to the value of Ifun), calculates the valid address of the memory reference, or increases or decreases the stack pointer. The resulting value is called the Vale

Access: Data can be written to or read from memory during the visit

Write back: Up to two results can be written to the memory.

Update PC: Sets the PC to the address of the next instruction.

3 seq Timing

The SEQ implementation consists of a combination of logic and two memory devices: a clock register, a random access memory (register file, instruction memory, and data memory). Combinatorial logic does not require any timing or control. This is a reasonable assumption for smaller memory (such as a register file), and for larger circuits, a special clock circuit can be used to simulate this effect. Since instruction memory is used only for reading instructions, we can consider this unit as a combinatorial logic.

4 Implementation of the SEQ phase

The register file has four ports, it supports simultaneous two reads (on ports A and B) and two writes (on Ports E and M). Each port has an address connection and a data connection, the address connection is a register ID, and the data connection is a set of 32 lines, either as the output word of the register file or as its input word. If the value on an address port is a special identifier of 0xF, the access register is not required.

4. 4 general principles of pipelining1 Calculation Line

In modern logic design, the circuit delay is calculated as a slight second, which is 10 of the negative 12 second.

2 detailed description of pipeline operation

To better understand how the pipeline works, take a closer look at the timing and operation of the pipelined calculations. Figure 4-34 is a three-stage pipeline diagram, the pipeline phase between the instruction transfer is controlled by the clock signal "every 120ps, the signal from 0 to 1 start the next set of pipeline stage calculation."

Information Security System Design Foundation Sixth Week study summary