Sixth chapter Memory Hierarchy
6.1.1 Random access memory RAM
Features of SRAM and DRAM memory:
As long as there is power, SRAM will remain the same, unlike DRAM, it does not need to be refreshed. SRAM is faster to access and more resilient to interference, at the cost of more expensive SRAM and greater power consumption.
Non-volatile memory rom
Ram loses information after a power outage, and the ROM can hold information even when it is powered off. Some of the types in ROM are both readable and writable, but are collectively referred to as read-only memory.
ROM is distinguished by the number of times they can be reprogrammed and the mechanisms used for reprogramming:
Programs stored in ROM devices are often referred to as firmware , a computer system is powered on, the firmware runs, and some systems provide a small amount of basic input and output functions in the firmware, such as PC and BIOS. Complex devices also rely on firmware to translate I/O input and output requests from the CPU.
accessing main memory
A bus is a set of parallel conductors that can carry addresses, data, and control signals.
1. Static RAM
SRAM stores each bit in a bistable memory unit. Each unit is implemented using a six-crystal circuit. This circuit has such a property that it can remain in one of the two different voltage configurations or States without a period of time. Any other state is unstable-from an unstable state, the circuit moves quickly to one of the stable states. Such a memory unit NVC the inverted pendulum.
2. Dynamic RAM
DRAM stores each bit as a charge to a capacitor. This capacitance is very small, usually only about 30 milli-tiny Faraday. DRAM memory can be manufactured very tightly, but unlike SRAM, DRAM memory cells are very sensitive to interference. When the voltage of the capacitor is disturbed, it will not be restored. Exposure to light can cause a change in the capacitance voltage. As long as there is power, SRAM will remain unchanged, unlike DRAM, which needs to be constantly refreshed. SRAM storage is faster than DRAM. SRAM is insensitive to interference such as light and noise. The cost is that the SRAM unit uses more transistors than the DRAM unit, so it is less dense, more expensive, and consumes more power.
3. The traditional DRAM
The cells in a DRAM chip are divided into D-units, each of which consists of a W DRAM unit. A DXW dram stores the DW bit information in total.
4. Memory Module
The DRAM chip is packaged in a memory module and is plugged into the expansion slot on the motherboard.
The most common packaging consists of a 168-pin dual-inline memory module that transmits data to the storage controller and out-of-memory data from a 64-bit block, and also includes a 72-pin single-column inline memory module that transmits data in 32-bit blocks.
5. Enhanced DRAM
Each is based on a traditional DRAM unit, and some optimizations have been made to improve the speed of access to the basic DRAM unit.
Fast-page mode dram:
The traditional DRAM copies a whole line of the superclass into its internal buffer, uses one, and discards the remaining.
Extended Data output dram:
An enhanced form of FPM dram, which allows individual CAS signals to be closer in practice.
Synchronous DRAM:
SDRAM is able to output the contents of a cell more quickly than those of asynchronous memory.
Double Data rate Synchronous DRAM:
Ddrsdram is an enhancement of SDRAM, which doubles the speed of DRAM by using two clock edges as a control signal.
Rambus DRAM:
This is another proprietary technology that has a higher maximum bandwidth than the DDR SDRAM.
Video RAM:
It is used in the frame buffer of the graphics system.
6.1.2 Disk storage
1. Disk Manufacturing
Each surface consists of a set of concentric circles called tracks (track), each of which is divided into a set of sectors (sector), each sector containing an equal number of data bits (usually 512 bytes), which are encoded in magnetic materials on the sector. The sectors are separated by some gap (GAP), and no data bits exist in these gaps. The Gap store is used to identify the format bits of the sector.
2. Disk capacity
Disk capacity is determined by the following technical factors:
Recording density
Track density
Surface density
Side note: For units associated with DRAM and SRAM capacity, usually k = 210,m = 220,g = 230, for units of I/O device capacity such as disks and networks, usually k = 103,m = 106,g = 109.
3 disk operation
(1) All reading and writing heads are located on the same cylinder at any time.
(2) At the end of the transmission arm read/write head on the disk surface height of about 0.1 microns on a thin layer of air cushion on the fly, the speed of about 80km/h. The disk reads and writes data as a block of sector size.
(3) The access time of the sector is composed of three main parts:
1. Seek time: In order to read the contents of a target sector, the drive ARM positions the read/write head first on the track containing the target sector. The required time is the seek time, approximately equal to the maximum rotation time.
2. Rotation time (rotational latency): After locating the desired track, the drive waits for the first bit of the target sector to rotate below the read/write header.
Tmax rotation = 1/maximum rotational number rate
Tavg rotation = (Xtmax) rotation
3. Transfer time: Tavg transfer = (1/MAX rotation) x (1/Average number of sectors per track)
Logical Disk Block
Modern disk construction is complex and has multiple disk faces, which have different recording areas. To hide such complexity from the operating system, modern disks simplify their construction to a sequence of logical blocks of a B sector size, numbered 0,1,2,... b-1. The disk has a small hardware/firmware device called a disk controller that maintains a mapping relationship between the logical block number and the actual (physical) disk sector.
Anatomy of connecting to an I/O device accessing a disk commercial disk
6.1.3 Solid-State Drive SSD
Disk Construction: Disk byPlatters
The surface is covered with magnetic recording material, and the center has a rotatable spindle
, the rotational rate is about 5400-15000 per minute. Each surface of the disk is a set of concentric circles called tracks, each of which is divided into a set of sector
, the sectors are separated by some gaps, and the gap stores the formatted bits used to identify the sectors. 6.2 Local Sex
Local principle: Time locality, spatial locality, ability to understand the last section of p429 "Memory Mountain"
A well-written computer program often has good locality, that is, they tend to refer to data items that are adjacent to other recently referenced data items, or to the data item itself that has recently been referenced. This tendency, called the principle of locality, is a persistent concept
(1) Time locality: In a program with good time locality, the memory location that has been quoted once is likely to be referenced more than once in the near future
(2) Spatial locality: In a program with good spatial locality, if a memory location is referenced once, then the program is likely to refer to a nearby memory location in the near future
A program that has good locality is much faster than the local program. Local Command locality
Logical Disk BLOCK:
Modern disks treat the fabric of the disk as a sequence of logical blocks of sector size B, and the disk controller maintains a mapping between logical block numbers and actual disk sectors. The logical block number can be identified as a disk face, track, sector triples, the unique identification of the corresponding physical sector. Memory can be considered as a byte array, and disks can be considered as block arrays.
Connect to I/O devices: All I/O devices are connected to the CPU and main memory via the I/O bus. There are three different types of:
Universal Serial Bus: A wide range of usage standards for connecting various peripheral I/O devices.
Graphics card (or adapter): Contains hardware and software logic, representing the CPU on the display of the image.
Host Bus adapter: Connect one or more disks to the I/O bus, using a communication protocol defined by a special host bus interface.
Information Security System Design Foundation Seventh Week study summary