Information Security System Design Foundation Sixth Week study summary

Fourth Chapter processor Architecture

4.1 Y86 Instruction Set architecture

The instruction set architecture includes defining various state elements, instruction sets, and their encodings, a set of programming specifications, and exception event handling.

Programmer-Visible state: Each instruction in the Y86 program reads or modifies portions of the processor state.

8 Program Registers:%eax,%EBX,%ECX,%edx,%esi,%edi,%esp,%EBP. Stores a word.

Memory: Can be understood as a large array of bytes, saving the program and data. The Y86 uses the virtual address to refer to the memory location.

Physical Address: The hardware and operating system software are combined to translate the virtual address into reality, indicating that the data is actually stored in the location of the memory.

Status code stat, which indicates the overall state of the program execution.

Y86 directive: Basically a subset of the IA32 instruction set.

Instruction encoding

the first byte of each instruction indicates the type of the instruction. The high four bits are part of the code, and the fourth bit is the feature section. ! The important nature of the instruction set-byte encoding must have a unique interpretation.

Y86 exception

Y86 Program

No scaling addressing mode;

！ With "." The beginning of the word is the assembler command

YIS (instruction Set Simulator) is intended to Y86 the execution of Machine program code

Details of some Y86 directives

Two special instruction combinations need attention!

4.2 Logic Design and hardware control Language HCL

Logic gates

and &&.   OR | |. Not

Combinational Circuits--combine many logic gates into a single net to build compute blocks.

！ Two restrictions:

(1) The output of two or more logic gates can not be connected together, otherwise they may cause the line signal contradiction, may lead to an illegal voltage or circuit failure;

(2) This net must be non-ring. Loops can cause ambiguity in the function of the network calculation.

3. Combination of Word-level circuits and HCl integer expressions

An expression:

Understanding: The preceding selection expression, which can be any Boolean expression, is evaluated in order, and the first case with a value of 1 is selected. Allowing non-exclusive selection expressions makes the HCL more readable. The signals of the actual hardware multiplexer must be mutually exclusive.

Arithmetic/logic unit (ALU)

Collection relationships

Memory and Clock

Two types of storage devices:
(1) Register (register): store single bit or word, clock signal control register load input value.

(2) Random access Memory (memory): Store multiple words, use the address to select the Du or which word to write

sequential implementation of 4.3 Y86

1. Organize the processing into stages

Fetch--decode--execute------write back--update pc

(Processor infinite loop, perform these stages)

2. SEQ hardware structure, SEQ timing

The SEQ implementation consists of a combination of logic and two memory devices: a clock register (program counter and Condition code register) and a random access register (register file, instruction memory, and data memory).

！！ Follow these guidelines to organize your calculations:
The processor never needs to read the state updated by the instruction in order to complete the execution of an instruction.

3. Implementation of the SEQ phase

Constants are generally denoted in uppercase.

(1) Taking the finger stage

The reference stage includes the instruction memory hardware unit.

(2) Decoding and writeback phase (access to register file required)

(3 implementation phase

The execution phase includes the arithmetic/logic unit (ALU).

(4) The stage of the visit

The task of the visit phase is to read or write the program data.

The final function of the memory stage is to calculate the status code stat from the result of the instruction execution according to the Icode, Imem_error, instr_valid value and the dmem_error signal generated by the data storage during the value phase.

(5) Update PC stage

The new value of the program counter is generated.

Reference material for the PDF version of the textbook

Experimental content:

1. Download the Y86 simulator

2. Build Yis Environment:

cd ~/Code/shiyanlou_cs413wget http://labfile.oss.aliyuncs.com/courses/413/sim.tartar -xvf sim.tarcd simsudo apt-get install tksudo ln -s  /usr/lib/x86_64-linux-gnu/libtk8.6.so /usr/lib/libtk.sosudo ln -s /usr/lib/x86_64-linux-gnu/libtk8.6.so /usr/lib/libtk.somake

3.YIS manual Download

4.YIS Test:

Information Security system design basics Sixth Week study summary