Integrated FPGA optimization

1 Speed and area

The overall optimization level will reach the speed and area of the RTL to take advantage of the logical topology.

For FPGA due to lack of knowledge in the backend, gate-level optimization. In general, higher speeds require higher parallelism and greater area, but in some special cases this is not the case. Because the layout and cabling of FPGA have the second order effect.

Until the layout is complete and routed. Tool will know the device congestion or wiring difficulties, but this time the actual logical topology has been submitted, assuming that our optimization option is set to speed, then when the device is too crowded to layout routing, the layout and Routing tool will generate additional logic. But the actual speed is slower. Therefore, when the resource utilization of the FPGA is close to 100%, the area optimization will get more speed.

2 with the resource sharing option provided by the integrated tool, it is possible to achieve some incompatible and similar operations, some of which may reduce the area, such as

Assign outdata=isel?idata1+idata2:idat2+idata3; When the resource sharing option is not set, the implementation is as follows:

After you open the resource sharing settings:

3 pipelining, again timing and register balancing

A register balance should not be used for non-critical paths.

b adjacent triggers with different reset types block the register balance.

C Constrains another synchronization register so that it is not affected by other register balances.

4 compilation of finite state machines

The state of the standard encoding is recognized by the compiler and optimized again.

For state machines, a gray code should be used to drive the asynchronous output, and the gray code is generated for example as seen:

The compiler will take its own initiative to remove the useless state. Don't be too high on the assumption that security is required. Turn on Safe mode. A reset signal is generated when the invalid state is generated.

5 black box, the black box is placed in the optimization module of the grid or layout of the agent. It is included in the implementation process of the later design total.

It is assumed that the time series model of I/O is given when a black box is required.

6 physical synthesis provides a close link between synthesis and layout diagrams.

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Integrated FPGA optimization