Introduction to the principle of full-digital PLL and the Design Code of OpenGL

With the development of digital circuit technology, digital PLL has been widely used in modulation and demodulation, frequency synthesis, FM stereo decoding, color sub-carrier synchronization, image processing, and other aspects. The Digital Phase-Locked Loop not only absorbs the advantages of high digital circuit reliability, small size, low price, but also solves the disadvantages of analog phase-locked loop, such as DC zero point drift, device saturation, and susceptible to changes in power supply and ambient temperature, in addition, it has the ability to process discrete sample values in real time and has become the development direction of the phase lock technology.

The so-called digital PLL refers to the PLL applied to digital systems. That is to say, all modules in the digital PLL are implemented by digital devices and are digital circuits. The advantage of the Digital Phase-Locked Loop is that the circuit is the simplest and most effective. It can use a crystal oscillator without voltage control, which reduces costs and improves the stability of the crystal oscillator. However, the disadvantage is that, like the analog phase-locked loop, once the benchmark frequency is lost, the output frequency immediately jumps back to the oscillator's own frequency. Another drawback is that when the frequency is adjusted, the output frequency may cause jitter. The larger the frequency difference, the larger the jitter is than the password, which is not conducive to some applications. With the development of large-scale and ultra-high-speed digital integrated circuits, the research and application of the Digital Phase-Locked Loop provides a broad space. The addition of the crystal oscillator and digital adjustment technology can increase the frequency tracking range without reducing the frequency stability of the oscillator, so as to improve the stability and reliability of the entire loop operation.

The phase-locked loop is a phase feedback control system. In the Digital Phase-Locked Loop, because the error control signal is a discrete digital signal, rather than analog voltage, therefore, the controlled output voltage changes are discrete rather than continuous. In addition, the components of the loop are all implemented using digital circuits. Therefore, this phase-locked loop is called the full digital phase-locked loop (PLL ). The Digital Phase-Locked Loop consists of the Digital Phase Detector, reversible counter, frequency switching circuit, and n-frequency divider. The reversible counter and the N-divider clock are provided by the external crystal oscillator. VCO is not used to greatly reduce the effect of temperature and power supply voltage changes on the loop. At the same time, the use of programmable chips in the system is conducive to improving the integration and reliability of the system.

The first-order digital phase-locked loop consists of the phase detector, the K-mode reversible counter, the pulse addition and subtraction circuit, and the N-counter division. The clock of the K mode changing counter and the pulse addition and subtraction circuit are MFC and 2nfc respectively. Here, FC is the center frequency of the loop. In general, both m and n are integers of 2. In this design, two clocks use the same system clock signal.

When the loop is out of lock, the phase difference between the input signal (FIN) and the output signal (fout) is compared, and the count direction control signal (dnup) of the K mode change reversible counter is generated ); the K mode-changing reversible counter adjusts the Count value according to the control signal (dnup) in the counting direction. The dnup is used to reduce the count for a high value. When the Count value reaches 0, It outputs the borrow signal ); when the counter value reaches the preset K-mode value, the carry pulse signal (carryo) is output. The pulse addition and subtraction circuit is based on the carry pulse signal (carryo) and the bitwise pulse signal (borrow) in the circuit output signal (idout) Pulse increase and deduct operations to adjust the frequency of the output signal; repeat the above adjustment process, when the loop enters the locked state, the output se of the exclusive OR gate phase detector is a square wave with a duty cycle of 50%, while the K-mode reversible counter periodically generates the carry pulse output carryo and the back-space pulse output borrow, this causes the output of the pulse addition and subtraction circuit to periodically add and deduct half of the pulse. In this way, there is no impact on the output frequency. It is precisely based on this principle that the noise with equal probability can be easily removed.

The source code of the all-digit Phase-Locked Loop is verified by the simulation.

Module DPLL (reset, CLK, signal_in, signal_out, Syn );

Parameter para_k = 4;

Parameter para_n = 16;

Input reset;

Input CLK;

Input signal_in;

Output signal_out;

Output SYN;

Reg signal_out;

Reg dpout;

Reg delclk;

Reg addclk;

Reg add_del_clkout;

Reg [7:0] up_down_cnt;

Reg [2: 0] cnt8;

Reg [8:0] cnt_n;

Reg SYN;

Reg dpout_delay;

Reg [8:0] cnt_dpout_high;

Reg [8:0] cnt_dpout_low;

/***** Phase detector *****/

[Email protected] (signal_in or signal_out)

Begin

Dpout <= signal_in ^ signal_out;

End

/***** Synchronization establish detector *****/

[Email protected] (posedge CLK or negedge reset)

Begin

If (! Reset) dpout_delay <= 'b0;

Else dpout_delay <= dpout;

End

[Email protected] (posedge CLK or negedge reset)

Begin

If (! Reset)

Begin

Cnt_dpout_high <= 'b0; cnt_dpout_low <= 'b0;

End

Else if (dpout)

If (dpout_delay = 0) cnt_dpout_high <= 'b0;

Else

If (cnt_dpout_high = 8 'b11111111) cnt_dpout_high <= 'b0;

Else cnt_dpout_high <= cnt_dpout_high + 1;

Else if (! Dpout)

If (dpout_delay = 1) cnt_dpout_low <= 'b0;

Else

If (cnt_dpout_low = 8 'b11111111) cnt_dpout_low <= 'b0;

Else cnt_dpout_low <= cnt_dpout_low + 1;

End

[Email protected] (posedge CLK or negedge reset)

Begin

If (! Reset) Syn <= 'b0;

Else if (dpout &&! Dpout_delay) | (! Dpout & dpout_delay ))

If (cnt_dpout_high [8: 0]-cnt_dpout_low [8: 0] <= 4 | cnt_dpout_low [8: 0]-cnt_dpout_high [8: 0] <= 4) Syn <= 'b1;

Else SYN <= 'b0;

End

/***** Up down couter with Mod = K ****/

[Email protected] (posedge CLK or negedge reset)

Begin

If (! Reset)

Begin

Delclk <= 'b0;

Addclk <= 'b0;

Up_down_cnt <= 'b00000000;

End

Else

Begin

If (! Dpout)

Begin

Delclk <= 'b0;

If (up_down_cnt = para_K-1)

Begin

Up_down_cnt <= 'b00000000;

Addclk <= 'b0;

End

Else

Begin

Up_down_cnt <= up_down_cnt + 1;

Addclk <= 'b0;

End

End

Else

Begin

Addclk <= 'b0;

If (up_down_cnt = 'b0)

Begin

Up_down_cnt <= para_K-1;

Delclk <= 'b0;

End

Else

If (up_down_cnt = 1)

Begin

Delclk <= 'b1;

Up_down_cnt <= up_down_cnt-1;

End

Else

Up_down_cnt <= up_down_cnt-1;

End

End

End

/***** Add and delete CLK *****/

[Email protected] (posedge CLK or negedge reset)

Begin

If (! Reset)

Begin

Cnt8 <= 'b000;

End

Else

Begin

If (cnt8 = 'b111)

Begin

Cnt8 <= 'b000;

End

Else

If (addclk &&! Syn)

Begin

Cnt8 <= cnt8 + 2;

End

Else

If (delclk &&! Syn)

Cnt8 <= cnt8;

Else

Cnt8 <= cnt8 + 1;

End

End

[Email protected] (cnt8 or reset)

Begin

If (! Reset)

Add_del_clkout <= 'b0;

Else

Add_del_clkout <= cnt8 [2];

End

/***** Counter with Mod = n ******/

[Email protected] (posedge add_del_clkout or negedge reset)

Begin

If (! Reset)

Begin

Cnt_n <= 'b0000;

Signal_out <= 'b0;

End

Else

Begin

If (cnt_n = para_N-1)

Begin

Cnt_n <= 'b0000;

Signal_out <= 'b0;

End

Else

If (cnt_n = (para_N-1)/2)

Begin

Signal_out <= 'b1;

Cnt_n <= cnt_n + 1;

End

Else

Cnt_n <= cnt_n + 1;

End

End

Endmodule

DPLL is composed of Phase Detector mode K addition and subtraction counter pulse addition and subtraction circuit to synchronously establish the detection circuit module n divider.

Center frequency of the entire system (that is, twice the code rate of signal_in and signal_out)

Is CLK/8/n. the K value of the modulo K addition/subtraction counter determines the accuracy and synchronization establishment time of DPLL. The larger the K, the longer the synchronization establishment time and the higher the synchronization accuracy. on the contrary, it is short and low.

Introduction to the principle of full-digital PLL and the Design Code of OpenGL