iTOP-4412 Embedded Development Board IOREMAP Control GPIO Registers

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When a GPIO register is converted through the Ioremap function, it is possible to control the physical address (the actual address of the register) by directly controlling the virtual address, thus realizing the Gpio read and write and any other functions.

Basic knowledge Required
Virtual Address and Physical address
Memory Management Unit Concepts
Loading of Linux driver modules

Main content
The register documentation for GPIO is described in detail and explained
The use of function Ioremap
Using IOREMAP to achieve control of GPIO

Hardware
Take the LED2 (LED near the buzzer) as an example to introduce the schematic and corresponding registers in the datasheet.
Schematic diagram
Open the backplane schematic PDF document, as shown in, select LED2, the network designator is kp_col0.

By looking up the network designator kp_col0, find kp_col0 on the connector as shown in.

Open the core Board PDF document, find the network designator kp_col0, find the gpio corresponding to the exnoys4412 chip,
As shown in.

As shown, the gpio corresponding to this pin is gpl2_0.
Open 4412 Datasheet, find the corresponding section of the Gpio, in the sixth chapter.

Register
In the sixth chapter there is a corresponding subsection "6.2 Register Description", in "6.2.1 registers Summary"
The GPL2 corresponding registers can be found, as shown in.

As shown, by reading the Register's descriptive text, it is clear that the register to be controlled is gpl2con (with
Registers), Gpl2dat (data register, corresponding output mode, register write 0 output low, write 1 output high
Level), Gpl2pud (pull-up and drop-down configuration, output requires pull-up), several other registers do not need to be used, default
Can.
The register address is generally composed of a base address and an offset address, and three registers can be found by "offset" in
The offset addresses of the gpl2con,gpl2dat,gpl2pud are 0x0100,0x0104,0x0108, respectively.
The maximum number of GPIO registers in the exnoys4412 is 32 bits, which can also be 16-bit or 8-bit, which
Required for register operation. Three registers can be found by "Reset Value" in
The value after the reset of the Gpl2con,gpl2dat,gpl2pud is 0x0000_0000,0x00,0x5555, that
The values of these registers are 32-bit, 8-bit, and 16-bit respectively.

Register Gpl2con
Search for the keyword "Gpl2con" in datasheet, as shown, you can find the base address of this register is
0x1100_0000. Then the physical address of the Gpl2con register PHY = 0x11000000 + 0x0100.

LED2 the corresponding Gpio is the Bit0 in GPL2, then find Gpl2con[0] (in the table, under
can be found) as shown in.

As shown, the Gpl2con register of [3:0] This low four-bit write 0x0 is the input mode, 0x1 is the output mode
Expression LED2 obviously needs to be configured as output mode, then the bit[3:0 of the Gpl2con register needs to write 0x1.

Register Gpl2dat
Search for the keyword "gpl2dat" in datasheet, as shown, you can find the base address of this register is
0x1100_0000. Then the physical address of the GPL2DAT register PHY = 0x11000000 + 0x0104.

Through the Description section, you can see the English "when configuring as output port,
The pin state should is same as the corresponding bit. " "IO is configured as
Output mode, write 0 in the register output low, write 1 output High ". So the bit of the Gpl2dat register
0-bit write 0 light is off, write 1 is bright.

Register Gpl2pud
Search for the keyword "gpl2pud" in datasheet, as shown, you can find the base address of this register is
0x1100_0000. Then the physical address of the GPL2PUD register PHY = 0x11000000 + 0x0108.

As shown, the "Bit" section is described first, "[2n + 1:2n] n = 0 To7" means n can take 0-7, respectively
Corresponds to 8 pin foot, n=0,2x0:2x0+1, is bit[0,1],n=1,2x1:2x1+1, is bit[2,3] in turn class
Push. Gpl2[0] n=0, need to operate on bit[0,1].
Here's one thing to note, as shown in the red box "Disables" should be enables, which is Samsung
A small error in the datasheet.

In summary, it is necessary to write 0x3 to the GPL2PUD register bit[0 1].

Summary of resource requirements in the code
The code requires the physical address of the register, the length of the register, and the value of the corresponding bit, as shown in the following table.

Software section
The main content of this section is software knowledge, before the introduction of code, will be a brief introduction to the Ioremap function, C language
The volatile keyword in the.
Ioremap function
The physical address and virtual address need to be mapped using the IOREMAP function to map the physical address to the virtual address
Then the virtual address operation is equivalent to the physical address operation, that is, directly to the register operation.
mapping functions
void *ioremap (unsigned long phys_addr, unsigned long size)
PHYS_ADDR: The starting IO address to be mapped
Size: The amount of space to map.
Unmap function
void Iounmap (void * addr)
Addr: The virtual address that is obtained after mapping.

Compiled Trivia-volatile keywords
In the C language, when the compiler optimizes for compilation, if it finds that the code that obtains the same variable multiple times does not have a
This variable is manipulated, for example:
int j = 10;
int call_first = j;
...... (large segment of code, but no operation on J)
int call_sec = j;

The compiler automatically assigns the value of the Call_first to call_sec without going back to the value of J. If registers are involved,
Then it's easy to make mistakes.
The address of the Register is involved, and the volatile keyword is provided in the C language. It can affect the result of compiler compilation, it will
Notifies the compiler that volatile variables are variable at any time, operations related to volatile variables, and do not
Compile optimizations to avoid errors. If the above variable uses the volatile definition, then each time it is used, it must be
J is read in the address, so the compiler generated executable code will re-read the data from the J address in the variable call_sec
In
Code
The code in this section requires knowledge of the previous documentation, as well as module registration and uninstallation.
Drive source
code file DRI_IOREMAP.C. The basics have been covered a lot, and the code has a lot of comments, no extra
Code analysis.
Sch:kp_col0→gpl2_0
/*gpl2→
Datasheet:gpl2con,gpl2dat,gpl2pud
ADD = Base Address+offset
Gpl2con = 0x1100_0000 + 0x0100 = 0x11000000 + 0x0100

S3c_gpio_cfgpin
Gpl2dat = 0x1100_0000 + 0x0104 = 0x11000000 + 0x0104
Gpio_set_value
Gpl2pud = 0x1100_0000 + 0x0108 = 0x11000000 + 0x0108
*/
/*gpl2_0→
Datasheet:gpl2con[0] gpl2dat[0] gpl2pud[0]
GPL2CON[0] [3:0]→output 0x0
Gpl2dat 0 or 1
Gpl2pud[0] 0x3
*/
/*
The registers are not necessarily all 32-bit, and there are 16 and 8-bit
Note that when you write a register
*/
#include <linux/module.h>
#include <linux/init.h>
#include <asm/io.h>
Volatile unsigned long virt_addr, phys_addr;//for storing virtual and physical addresses
Volatile unsigned long *gpl2con, *gpl2dat, *gpl2pud;//address for storing three registers
void Gpl2_device_init (void)
{
0X11000100 + 0x10 includes all IO PIN register addresses
PHYS_ADDR = 0x11000100;
0x11000100=gpl2con
Request a contiguous space of length 0x10 in the virtual address space
In this way, the physical address phys_addr to phys_addr+0x10 corresponds to the virtual address virt_addr to virt_addr+0x10
VIRT_ADDR = (unsigned long) ioremap (phys_addr, 0x10);
Specify the address of the register that needs to be manipulated
Gpl2con = (unsigned long *) (virt_addr + 0x00);
Gpl2dat = (unsigned long *) (virt_addr + 0x04);
Gpl2pud = (unsigned long *) (virt_addr + 0x08);
}
LED configuration function, configuring the GPIO registers of the Development Board
void Gpl2_configure (void)

{
//gpl2con Register, Bit0 set to 1, output mode
*gpl2con |= 0x00000001;
Gpl2pud Register, Bit[0:1] set to 0x3, pull-up mode
*gpl2pud |= 0x0003;
}
void gpl2_on (void)//lit LED
{
*gpl2dat |= 0x01;
}
void Gpl2_off (void)//off LED
{
*gpl2dat &= 0xfe;
}
Static int __init led_gpl2_init (void)//module initialization function
{
PRINTK ("init \ n");
Gpl2_device_init (); Implement the mapping of IO memory
Gpl2_configure ();//configure GPL2 to Output mode
gpl2_on ();
PRINTK ("led GPL2 open\n");
return 0;
}
static void __exit led_gpl2_exit (void)//module unload function
{
PRINTK ("Exit \ n");
Gpl2_off ();
Iounmap (void *) virt_addr);//Undo Mapping Relationship
PRINTK ("led GPL2 close\n");
}
Module_init (Led_gpl2_init);
Module_exit (led_gpl2_exit);
Module_license ("GPL");
Module_author ("dz20160510");
Module_version ("2016-05-10");

Compiling scripts
The compile script Makefile code is as follows.
#!/bin/bash
#通知编译器我们要编译模块的哪些源码
#这里是编译 read_gpio.c This file into an intermediate file read_gpio.o
Obj-m + = DRI_IOREMAP.O
#源码目录变量, here users need to choose the path according to the actual situation
#作者是将 Linux source Copy to the directory/home/topeet/android4.0 and unzip the
Kdir: =/home/topeet/android4.0/itop4412_kernel_3.0
#当前目录变量
PWD = $ (shell pwd)
#make naming by default looking for the first target
#make-C refers to the path where execution is invoked
#$ (kdir) Linux source directory, author here refers to/home/topeet/android4.0/itop4412_kernel_3.0
#$ (PWD) Current directory variable
#modules the action to perform
All
Make-c $ (Kdir) m=$ (PWD) modules
#make clean does this by removing the file with the suffix o
Clean
RM-RF *.O

Compiling Run Tests
After compiling, run the ITOP-4412 board minimum system, load the driver module, light up near the LED, uninstall
The module will be extinguished.

iTOP-4412 Embedded Development Board IOREMAP Control GPIO Registers