Learning and understanding of 4.RCC peripherals

RCC Clock module is not good understanding, the first contact I also confused, and I really mastered it is also relatively late, is that I learned to use Register control Development Board to really understand his operating principles and laws, but why I re-revised but placed in the forefront, because this is the whole embedded foundation, beginners are more difficult , but I still want to be able to grasp the best, because the real-time is very important to the embedded system, and the basis is to understand from the system clock to each of the modules you selected its clock frequency, understand this module for learning all the modules are useful, gossip not to say, into the topic:

At first look at this picture is not too complicated, in fact, when I first saw this picture is also yes, completely confused structure, but below I take you from shallow to deep to understand the picture.

(1) clock source (4 crystal oscillator source, 1 intermediary source)

HSI (RC): Internal high-speed crystal oscillator, ~8mhz

HSE (OSC): External high-speed crystal oscillator (related to circuit design, 25MHz)

LSE (OSC): External low-speed crystal (default is 32.768KHZ)

LSI (RC): Internal low-speed crystal oscillator, ~40khz

PLLCLK: Locked loop multiplier output, maximum frequency less than 72MHz, note: pllclk source HSE,HSE/2,HSI/2

(2) System clock Source

SYSCLK: System clock

SOURCE Hsi,pllclk,hse, if the CSS (Clock monitoring System) detects a HSE failure, SYSCLK = HSI;

(3) Main output clock source

HCLK: High performance bus clock (sysclk via AHB Prescaler, up to 72MHZ)

PCLK1: Peripheral 1 Zone clock (up to 36MHZ via APB1 Prescaler)

PCLK2: Peripheral 2 Zone clock (up to 72MHZ via APB2 Prescaler)

ADCCLK: ADC Peripheral Clock (PCLK2 via ADC Prescaler)

In addition to providing clocks to the corresponding peripheral regions, the APB1,APB2 peripheral clocks can also be assigned different timer clocks via the Timerx prescaler.

USBCLK: Universal Serial Interface Clock (PLLCLK via USB prescaler, equals 48MHZ)

RTCCLK: Real-time clock, source lsi,lse,hse/128

IWDGCLK: independent watchdog clock, source LSI

MCO: Output Internal clock

From the above, the Gpiod peripherals we mentioned earlier, as well as the clocks in the back usart,can, are not mentioned, why, in fact, they are contained in the PCLK1,PCLK2 two peripheral area clocks, that is, their clocks and the peripheral area of the clock is equal. The following is a diagram of 15.2.22 and 15.2.23 in the STM32FXXX firmware function library, which contains the corresponding area for all peripherals:

PCLK1 Clock Area:

PCLK2 Clock Area:

through the appeal of the two graphs can clearly know I in the first chapter of the running Lights clock enable the reason for the choice of APB2 peripherals, of course, I take stm32f10x as an example, if you use a different chip to check the corresponding register manual. Understand that these are actually the system clock master almost, below I will show the configuration of the embedded clock in Register control mode (library function operation is not very helpful to understand the clock configuration process, especially if it is simply called without understanding the contents of each function).

(4) System clock Configuration example (to use the HSE crystal, the last system clock is 50MHZ for example)

Note: The RCC register function can be referenced in the STM32 Chinese reference Manual 6.3 (connected product)     

UnsignedCharPLL =4;//PLL is a multiple of the set magnificationUnsignedChartemp =0;//1.HSE Clock Enable//Clock Control Register RCC->CRRCC-&GT;CR &=1<< -;//Enable HSEWhile (! (RCC-CR) >> -));//Judging the HSE readiness Mark bit//2. Configure PLL,APB2,APB1,AHB//Clock Configuration Register RCC->CFGRRCC-&GT;CFGR |=0x00000400; //AHBCLK = SysTick, apb2clk = AHBCLK,APB1CLK = Ahbclk/2PLL-=2; RCC-&GT;CFGR |= pll<< -;//Reference Register function table, 0010~4 times, increase in sequence, up to 9 times times maximumRCC-&GT;CFGR |=3<< -;//HSE/2 as input to the PLL//3.FLASH Pre-access-clock configuration//Flash pre-access register FLASH->ACR//Note: See the STM32 Flash programming, but one thing to note, the system clock is larger than 30MHZ must be configured, the default 24MHZ after the need to configureFLASH-&GT;ACR |=0x32;//Open Pre-access, 2 wait cycles//4.PLL Enable//Clock Control Register RCC->CRRCC-&GT;CR |=1<< -;//PLL Enable while(! (rcc->cr>> -));//to determine the PLL enable flag bit//5.PLL as System clockRCC->cfgr | =0x00000002;//PLL as System clock while(temp!=0x02)//PLL succeeds as system clock, flag bit{Temp= rcc->cfgr>>2; Temp&=0x03;} 

The clock initialization setting of the general peripheral of the clock is completed by the above method, and the system clock 50MHZ,APB2 peripheral clock 50MHZ,APB1 Peripheral clock 25MHZ is understood, and the time spent in subsequent program operation is accurately known by calculation. This is useful for the entire embedded learning and subsequent understanding of the real-time operating system.

Learning and understanding of 4.RCC peripherals