Link Analysis Between S3C2440 and SDRAM and NAND and nor

 

Reprinted from: http://tanatseng.blog.163.com/blog/static/17499162920101022323130/

S3C2440 has 27 address lines ADDR [26:0], 8 chip selection signal nGCS0-nGCS7, corresponding to the bank0-bank7, when accessing bankx address space, ngcsx pin for low level, select peripherals.

2 ^ 27 = 2 ^ 7*2 ^ 10*2 ^ 10 = 128 Mbyte

8*128 Mbyte = 1 Gbyte

Therefore, the total addressing space of S3C2440 is 1 Gbyte.

There are few 32-Bit Single-Chip SDRAM on the market. Generally, 2 16-bit SDRAM slices are used to expand to 32-bit SDRAM.

The sdarm is hybri57v561620f, 4 Mbit * 4 bank * 16, 16 Mbyte in total? (Explained later)

The two hy57v561620f are connected together to form 64 m × 32bit SDRAM

First, understand the addressing principle of SDRAM.

The internal structure is a storage array. You can think of it as a table. Like table search, you can specify rows and columns to find the storage unit you need. This table is called a logical bank. Currently, only four banks are used for the SDRAM. The addressing process is to first specify the Bank address, then the row address, and finally the column address. This is the addressing principle of SDRAM. The storage array is as follows:

View the information of hy57v561620f, which has

13 line address line RA0-RA12

9-column address line CA0-CA8

2 Bank Selection Line BA0-BA1 (4 bank selection)

The address pins of the SDRAM are reused. When reading and writing the SDRAM storage unit, the operation is to input the Read and Write addresses to the chip twice, each of which is input by the same group of address lines. The addresses sent to the chip twice are called the row address and column address respectively. They are locked to the internal row address latches and column address latches of the chip.

/RAS is the line address lock signal, which stores the line address lock in the line address lock inside the chip;

/CAS is the column address lock signal, which locks the column address in the internal column address latches of the chip.

After being attached to bank6, the physical address of the SDRAM is 0x30000000.

Address connections include:

 

 

 

Lnscs0 is connected to ngcs6, that is, it is connected to bank6, so the physical address of SDRAM starts from 0x30000000

Why does laddr2 connect to A0?

@ The addressing space of the CPU is still operated in 8 bits per byte

@ Because SDRAM is connected to 32-bit memory, that is, 4 bytes, the minimum unit is 4 bytes, which facilitates 32-bit read/write operations.

 

Why does laddr24/25 connect to ba0/1?

@ BA1: ba0 is the highest bit of SDRAM. select one of the four banks.

@ Laddr0 ~ Laddr25, a total of 26 address lines, addressable (26 to the power of 2) 64 MB

 

Why is a bank4mb instance with a capacity of 8x4 = 32 MB instead of 4 MB x 4 bank = 16 MB?

@ 13 line address lines + 9 column address lines = 22 (4 MB ). In addition, a storage unit of hy57v561620f is two bytes (16 bits), which is equivalent to 23 address lines.

In norflash, a0 is connected to the CPU's laddr1, so the minimum addressing unit of norflash is 2 bytes (16 bits), in fact only a0 ~ A19 is valid because the nor itself has 2 MB, the power of 2 is equal to 1 MB, and the nor itself is 16 bits (2 bytes ), so 1 MB × 2 is the nor size.

@ 26: ngcs0 is connected to bank0. Therefore, the physical address of nor starts from 0x00000000.

 

 

From the wiring, we can see that NAND is a little special. He didn't access it through the address line of the CPU, so he answered why the 1 gb nand can be connected. Of course, he didn't select the bank line either, naturally, there is no physical address, so I guess that NAND is identified by the hardware itself, that is, whether the OM switch is enabled by nor or NAND, this also seems to verify the ing between the two startup modes in the Data Manual. For the NAND startup mode, refer to the preceding log

 

0x4000_0000-0x4000_0fff

----- The 4 K bytes are the stepingstone mentioned above. 0x4000_0fff_0x4800_0000 is useless.

0x4800_0000-0x6000_0000

----- This space is a special function register. You find that all registers are in this range.

0x6000_0000-0xffff_ffff

----- It is still not used.

Theoretically, the addressable space is 4 GB (32 to the power of 2), but 3 GB of space is reserved for registers inside the processor and other devices, the external addressable space is only 1 GB, that is, 0x00000000 ~ 0x3fffffff, there should be a total of 30 address lines. The 1 GB space, the 2440 processor divides it into eight parts based on the features of the supported device, each of which has 128 MB, which is also called a bank. For ease of operation, 2440 independently gives each bank a chip selection signal (ngcs7 ~ Ngcs0 ). In fact, these eight chip selection signals can be seen as the results of address decoding by the top three of the 30 IP lines in the 2440 processor. Because the address information represented by the three address lines has been transmitted by eight chip selection signals, the actual address line output by the 2410 processor is only A26 ~ A0

Due to its own characteristics, nandflash does not have the function of running programs. However, S3C2440 implements the startup code that can run and store in external nandflash through the internal SRAM cache called "steppingstone. Its mechanism is: when it is detected that it is started by nandflash, the system will automatically load the first 4 K bytes of data in nandflash to steppingstone, and then map the steppingstone to bank0, therefore, the system starts to run the program from steppingstone, thus implementing the nandflash self-starting function of S3C2440. This process is automatically completed by the system without human intervention. After the system is started, steppingstone's SRAM can be used for other purposes.