MiS603 Development Board Chapter 11th CY7C68013A Slave FIFO return transmission

MiS603 Development Team

Date: 20150911

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MiS603 Development Board Chapter 11th CY7C68013A Slave FIFO return transmission

CY7C68013A provides a powerful and flexible way to communicate with external interfaces, both in slave FIFO and Gpip mode. Since this tutorial uses the FPGA+CY7C68013A scheme, the slave FIFO mode is used for transmission, and this section begins with a detailed explanation of SLAVEFIFO transmission.

11.1 Application Scenario Analysis

USB2.0 interface is a very convenient use of the communication interface, all computers with USB interface, and theoretical bandwidth in 480mb/s, suitable for many data transmission occasions, such as data acquisition, video image transmission.

11.2 Slave FIFO hardware structure

, describes the hardware structure of the cy7c68013a slave FIFO:

1), Slavefifo with 4 endpoints, respectively, EP2/EP4/EP6/EP8

2), clock with internal clock 48mhz/30mhz two kinds of choice, or with external clock 5~48mhz input

3), the external port through a number of control signals to achieve the control of communication timing

4), the data port can be configured to the maximum 16bit bit width

Describes the wiring diagram of the cy7c68013a and external devices in the slave FIFO mode, as you can see, EXT Master is the FPGA

11.3 Slave FIFO Timing Analysis

Describes the asynchronous communication timing, and synchronous communication timing, if the asynchronous timing is used as long as the signal slrd and SLWR can be, but asynchronous timing needs to consider sampling and sampling period, that is, when the cy7c68013a work at the highest speed of 48MHZ, is unable to sample to 48MHZ asynchronous signal, So the speed, asynchronous timing is not synchronous timing fast. From there, you can compare the differences between asynchronous and synchronous transmissions. Asynchronous transmissions are controlled entirely by SLRD and SLWR, while synchronous transmissions are synchronized with IFCLK in SLRD or slwr active state. The example in this section also uses synchronous timing.

Before you perform a specific synchronous timing analysis. First, to understand the cy7c68013a of each pin corresponding to the function.

The IFCLK:FX2 output clock, which can be used as a synchronous clock for communication.

FLAGA/FLGAB/FLAGC/FLAGD:CY7C68013A The status information of internal FIFO, such as full, empty flag, etc. The functions of these state information can be implemented by subsequent programming.

SLCS:FIFO chip Select Enable signal, controlled by external logic, low-level active.

Sloe:fifo the output enable signal, when it is invalid, the data on the data line is invalid.

SLRD:FIFO read signal, when using synchronous timing transmission, in the case of slrd active state, the data with the IFCLK clock from the FIFO read out.

Slwr:fifo write the signal, when using synchronous timing transmission, in the case of SLWR active state, the data with IFCLK clock write FIFO.

Pktend: Packet end signal. Normally, when a signal is written to the cy7c68013a, the data is automatically packaged for transmission when the number of bytes written to the FIFO endpoint equals the pre-set packet size. When the data is written, less than the set packet size, just after the data transfer is complete, define this signal, the data is automatically packaged and transmitted.

FIFOADR: Address control side, select the internal cy7c68013a four FIFO. Where fifoadr=2 ' b00, corresponds to Endpoint 2, that is, the address of the internal FIFO. fifoadr=2 ' B01, corresponding endpoint 4,fifoadr=2 ' B10 corresponding endpoint 6,fifoadr=2 ' B11 corresponds to Port 8.

FD: Data cable. Configurable 16bit bit width or 8bit bit width.

The following analysis, respectively, synchronous transmission mode read and write timing.

1. Synchronous transmission Slave FIFO write mode:

such as the state machine (the state machine from the official manual, detailed reference to the official Fx2+techrefmanual manual). Its standard write timing is:

Initial state: When the Write event occurs, enter State 1;

? State 1: The state determines the address that the Fifoadr points to, selects the endpoint number, completes, enters the state 2;

? State 2: According to the selected FIFO full, empty flag bit, determine whether to write data, if the FIFO full state, wait in that state until the full state is invalid, enter the state 3;

? State 3: Keep the Write signal slwr valid, will be written to the data into the data line, the continuation of a IFCLK clock, into the state 4;

? State 4: If you continue to write data, go to state 2, otherwise the write completes, enter the idle state.

By default, the Full,empty,slwr,pktend are active low, and several timing diagrams correspond to the following:

Scenario One: No data in FIFO, write data when empty

, select Endpoint 8, after a single cycle, to determine that FLAGB is always high, FLGAC is always low, that is, endpoint 8 does not have data, at which time data can be written. When the SLWR low is active, the IFCLK rising Edge writes the data n. After writing, the FLGAC is high, which means that the endpoint is non-empty. At this point, the FLAGB still invalid, that is, the data can continue to write, SLWR again pull down, ifclk the rising edge of writing data n+1.

Case two: FIFO non-Empty, and FIFO is not full, the data is written

As can be seen, at this point in Endpoint 8, the Flgab clock is high, invalid state, that is, non-empty state, FLGAC is also invalid, that is, the endpoint data is not full. Continuous write, when 512 bytes are written, the pre-set packet bytes are reached, cy7c68013a the data is automatically packaged and transmitted. The process is automatically completed by the hardware, the external logic according to the time series, after writing bytes, FX2 hardware automatically package data for high-speed transmission.

Scenario Two: Data in FIFO is full

As can be seen from the above, when the data is full, the FLAGB full flag bit low active, the data does not reach the set of data packets, can be pulled through the low pktend signal to package transmission. However, the flgab continues low and the data cannot be written when the write signal is valid again.

2. Synchronous transmission Slave FIFO read mode:

Since the synchronous transmission write has a fixed pattern, of course, the reading must follow the corresponding timing. Its state transition diagram is as follows:

As can be seen from its official standard timing, the following procedures are included:

Initial state: When the Read event occurs, enter State 1;

? State 1: The state determines the address that the Fifoadr points to, selects the endpoint number, completes, enters the state 2;

? State 2: When the data bits in the endpoint are empty, the state is maintained, and when the data in the endpoint is not empty, it goes to state 3;

? State 3: To keep the write signal slrd effective, from the data line to collect data, continuous a IFCLK clock, data acquisition is completed, FIFO internal reading pointer automatically added 1, into the state 4;

? State 4: If you continue to read the data, enter the status 2, otherwise the write completes, enters the idle state.

Similarly, each status signal or control signal, the default low-level active, its official supply of several reading sequence diagram is as follows:

Scenario One: Non-empty FIFO, normal read operation

It can be seen that the state 2 o'clock, select the endpoint 2FIFO,FLAGC continuous high level, indicating that the FIFO in the endpoint 2 has data, can read and write, when the sloe is valid, enable SLRD, in the IFCLK rising edge, read the data on the FD Bus, FX2 corresponding FIFO internal pointer automatically accumulate, Be prepared for the next read operation.

Scenario Two: FIFO is empty, no data

When the continuous read operation, the FLGAC valid state, the Sloe and SLRD are set to an invalid state, waiting for data in the FIFO to read the operation again, the data bus maintains a high impedance state.

11.4 Slave FIFO backhaul experiment

Through the previous sections of the slave FIFO detailed introduction, this section to complete a slave FIFO test. The data is sent via the host computer, and the cy7c68013 data is transmitted to the FIFO in the FPGA. The FPGA returns the data in the FIFO to the FIFO in 68013 by cy7c68013, and the host computer can fetch the data in the FIFO. The other part of the FIFO data, through the serial port to the debugging assistant, compare the data two times.

11.5 USB Firmware Source code Analysis

In the complete development package provided by Cypress, the programming framework for firmware is included, and many firmware programs are available for direct application. The development of the firmware can be accomplished by using the user directly, or by adding a small amount of code on the basis of the original framework. A hook function is provided inside the framework, and the user adds their own code to the hook function to complete the programming.

When the firmware resets the power on, it initializes some global variables, then calls the initialization hook function td_init (), interrupts, waits for device re-enumeration to complete, and finally enters the while (1) Loop statement to perform the task scheduling. Below, the first simple introduction of the framework of firmware development, and then combined with the specific source code, analysis under the firmware development process, the configuration of key registers.

? Firmware General Framework Analysis

Open the firmware engineering file for the MIS603 Development Board, where you can see that the project on the left is shown below. As can be seen, the project mainly contains FW.C and slave.c files.

The fw.c file is the root of the entire USB, and the USB protocol is done here, including power-up enumeration, re-enumeration, wake-up and invoke programs, and so on. This project document is provided by the development package provided by Cypress company, if not necessary, try not to modify the content.

The slave.c file is a written file of the user's own code, usually where the bread contains the registers, clocks, breakpoints, etc. that need to be configured to transmit data. Of course, this program is not all required by the user to write, you can copy the official firmware development project, and then modify it from there. The user can find it from the installed Cypress development package, the path is: D:\Cypress\USB\CY3684_EZ-USB_FX2LP_DVK\1.0\Firmware. This folder is a firmware development routine for different applications provided by Cypress. Users only need to modify the official of the Can.

As for the other called files, you can see from the following table:

Ezusb. Lib

EZUSB Library file

EZUSB.h

Ezusb header File

Fx2regs.h

FX2 Register header file

Fx2.h

predefined, macro, and function declarations

Fw.c

Firmware Framework source File

Dscr.a51

A list of USB descriptors that users can modify

Usbjmptb.obj

Break Jump function Target file

Syncdly.h

Synchronization delay, defines the program short delay function Syncdelay

Intrins.h

C51 some data types and function definitions

Intr.c

External interrupt Processing file

Of course, all of the above documents may not be required in the project. After opening the firmware program, click Compile, many people may not be able to compile immediately, this is due to the path of the project file changes, resulting in the inability to compile all the files. The path you need to modify here contains the following two windows. After adjusting these paths, click Compile again to make sure the compilation is correct and all files are involved in the project compilation.

When the compilation is complete, its compilation results are as follows:

After understanding the development process described above, the functions that continue to be understood include:

void Td_init (): This function is only called once after USB is started. This function mainly adds the initialization code of the USB data transfer, which is to be configured before transmission. With 68013 internal registers, the clock, FIFO, interrupt, etc. are configured.

void Td_poll (): User scheduler, where USB executes the function repeatedly during idle time, often putting code that executes repeatedly inside. Typically, the default method is used directly.

As for the other functions, it is not very important in this routine, so please refer to the official documentation for more explanations.

? USB Transfer Register Configuration

CY7C68013 is actually a 51-core microcontroller, said the microcontroller naturally to its operation, it involves register configuration. Therefore, it is an important step to configure the registers before transmitting the data effectively.

1. Set the clock register cpucs=0x10, where the Cpucs register is as follows:

Cpucs

? PORTCSTB---1 indicates that the rd# and wr# signals are generated when reading and writing port C, 0 does not generate read-write signals and defaults to 0.

? CLKSPD1,CLKSPD0---CPU clock settings. As shown in the following table:

? CLKINV---clock State reversal

? Clkoe---clock enable

2, PINFLAGSAB/CD (e602:e603): FLAGX PIN Configuration Register

Flaga,flagb,flagc,flagd reflects FIFO state selection. Each foot has the address/fixed two modes: If set to address mode, they all reflect fifoadr[1:0] feet current point of the State, wherein, Flaga reflect "programmable limit", FLAGB reflect "full" flag, FLAGC reflect "empty" flag, FLAGD does not exist , if set to fixed mode, they can be arbitrarily set to reflect any of the endpoints of any flag, without being limited to the state of the current point of the fifoadr[1:0] foot.

In the Slave FIFO mode, the pin FLAGA~FLAGD is used to define the state of the endpoint FIFO and can be flexibly programmed to implement the FLAGX settings, as shown in the following table.

Description

1. PF indicates FIFO programming state, EF indicates FIFO is empty, FF indicates FIFO is full

2. 0000 is index mode, others are fixed mode

3. PORTACFG: Port A configuration

1 Enable port a multiplexing pin, although SLCs appears in portacfg.6 position, when ifcfg1:0=11, Porta.7 multiplexing for SLCS,FLAGD also appears on the porta.7 pin, when portacfg.7 is set, porta.7 multiplexing is FLAGD output, when portacfg.6 and portacfg.7 are 1, porta.7 is multiplexed flagd. So when portacfg7:6=01, porta.7 is reused as SLCs.

4. Interface Configuration Register Ifconfig

IFCONFIG

? IFCLKSRC---0 external clock source, 1 internal clock source.

? 3048MHZ---0 ifclk clock is 30m,1 ifclk clock is 48M.

? Ifclkoe---ifclk clock output enable, 0 off, 1 open.

? Ifclkol---ifclk signal anyway, 0 not reversed, 1 reversed

? Async---GPIF synchronous or asynchronous operation, 0 synchronous, 1 async

? Gstate---GPIF status output Enable, 0 off, 1 Enable, pin PE0 PE1 PE2 and GPIF status Gstate0,gstate1,gstate2.

? IFCFG0,IFCFG1---Mode setting, which determines the port pin function.

5. EP2CFG/EP4CFG/EP6CFG/EP8CFG Endpoint 2,4,6,8 Configuration register

? VALID---0 endpoint is invalid and the 1 endpoint is valid.

? DIR---Endpoint direction, 0=out direction, 1=in direction, default endpoint 2, 4 bit in, end 6,8 as out.

? TYPE1,TYPE0---The endpoint type, as shown in the following table.

? Size---buffer sizes (port 2 and endpoint 6 only), 0=512 bytes, 1=1024 bytes

? BUF1,BUF0---The number of endpoint buffers (port 2 and endpoint 6 only).

6. Endpoint 2/4/6/8 FIFO configuration register

Ep2fifocfg/ep4fifocfg/ep6fifocfg/ep8fifocfg

? INFM1---1 indicates that the in endpoint is 1 full minus.

? OEP1---1 indicates that the out endpoint is empty plus 1.

? Autoout---1 means that data is automatically submitted out of the endpoint fifo,0 represents manual.

? Autoin---1 indicates that the in endpoint FIFO data is automatically submitted sie,0 represents manual.

? Zerolenin---1 means enable 0 length in endpoint packet, 0 means non-enable.

? Wordwied---Data width, 0 means 8bit,1 represents 16bit.

Other important registers you can refer to the official documentation. Of course, do not want to see the Chinese, recommend everyone a book "USB Development Manual", this book describes in detail the USB68013 all the use of methods.

Important program source code is as follows:

void Td_init (void)

{//called Once at startup

Cpucs = 0x10; clkspd[1:0]=10, for 48MHz operation, output clkout

Pinflagsab = 0x08; Flagd-ep2ef

Syncdelay;

PINFLAGSCD = 0xE0; Flaga-ep6ff

Syncdelay;

Portacfg |= 0x80;

IFCONFIG = 0xe3; For async? For sync?

Ep2cfg = 0xA0; Out bytes, 4x, bulk

Syncdelay;

Ep6cfg = 0xE0; In bytes, 4x, bulk

Syncdelay;

Ep4cfg = 0x02; Clear valid bit

Syncdelay;

Ep8cfg = 0x02; Clear valid bit

Syncdelay;

Syncdelay;

Fiforeset = 0x80; Activate Nak-all to avoid race conditions

Syncdelay; See TRM section 15.14

Fiforeset = 0x02; Reset, FIFO 2

Syncdelay; //

Fiforeset = 0x04; Reset, FIFO 4

Syncdelay; //

Fiforeset = 0x06; Reset, FIFO 6

Syncdelay; //

Fiforeset = 0x08; Reset, FIFO 8

Syncdelay; //

Fiforeset = 0x00; Deactivate Nak-all

Handle the case where we were already in AUTO mode ...

... for example:back-back firmware downloads ...

Syncdelay; //

Ep2fifocfg = 0x00; Autoout=0, wordwide=1

Core needs to see Autoout=0 to autoout=1 switch to arm ENDP ' s

Syncdelay; //

Ep2fifocfg = 0x10; Autoout=1, wordwide=1

Syncdelay; //

Ep6fifocfg = 0x4C; Autoin=1, Zerolenin=1, wordwide=1

Syncdelay;

}

11.6 FPGA Source Code Analysis

Module USB_FPGA (

Input ifclk_i,

inout [7:0] Fdata_b,

OUTPUT[1:0] Faddr_o,

Output Reg Slrd_o,

Output Reg Slwr_o,

Output Reg Sloe_o,

Input Flagd_i,

Input flaga_i

);

Parameter read1=0;

Parameter read2=1;

Parameter write1=2;

Parameter write2=3;

reg [1:0] usb_s=0;

Wire empty;

Wire [7:0] usb_tx;

Switching of bidirectional port data streams

Assign fdata_b= ((usb_s==write1) | | (USB_S==WRITE2)) ? Usb_tx:8 ' Hzz;

CY7C68013A EP2 and EP6 port switching

Assign Faddr_o = ((usb_s==read1) | | (USB_S==READ2)) ? 2 ' b00:2 ' B10;

88888888888888888888888888888888888888888888888888888888888888888888888888888888888

Read/write control logic

Always @ (*) begin

if (flaga_i&& (usb_s = = READ2)) begin//Read USB FIFO

Slrd_o <= 1 ' b0;

Slwr_o <= 1 ' B1;

Sloe_o <= 1 ' b0;

End

else if (flagd_i&& (usb_s = = WRITE2)) begin//write USB FIFO

Slrd_o <= 1 ' B1;

Slwr_o <= 1 ' b0;

Sloe_o <= 1 ' b0;

End

else begin//stop reading and writing

Slrd_o <= 1 ' B1;

Slwr_o <= 1 ' B1;

Sloe_o <= 1 ' b0;

End

End

Wire SYS_CLK;

reg [9:0]usb_cnt;

Assign sys_clk=~ifclk_i;

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Read/write State machine

Always @ (Posedge SYS_CLK) begin

Case (usb_s)

Read1:begin//This state 1 clock cycles switch the transmit port to the read

usb_s <= READ2;

End

Read2:begin//This status switch port

if (flaga_i);//usb FIFO non-empty data is always read

else if (usb_cnt>511)//If the FPGA FIFO is not empty, it enters write preparation

usb_s <= WRITE1;

End

write1:begin//This state 1 clock cycles switch the transmit port to write

usb_s <= WRITE2;

End

Write2:begin

if (flagd_i);//usb FIFO is not full read data from FPGA FIFO

if (empty) usb_s <= READ1; Until the read empty FIFO

End

Endcase

End

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Test the number of incoming and outgoing data

(*keep = "TRUE" *) wire[9:0] USB_CNT_DG;

Assign usb_cnt_dg=usb_cnt;

Always @ (Posedge SYS_CLK) begin

if (usb_s==read2&&flaga_i) usb_cnt<=usb_cnt+1 ' B1;

if (usb_s==write2&&flagd_i) Usb_cnt<=usb_cnt-1 ' B1;

End

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Internal delay Reset

reg [9:0] cnt=0;

Always @ (Posedge SYS_CLK) begin

if (!cnt[9]) cnt<=cnt+1;

End

Wire rst;

Assign RST =!cnt[9];

Wire full;

Wire [7:0] USB_RX;

Assign USB_RX = Fdata_b;

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Fifo

FIFO Fifo0 (

. CLK (SYS_CLK),//Input CLK

. RST (RST),//Input RST

. DIN (USB_RX),//input [7:0] Din

. Wr_en (~slrd_o && (~full)),//input Wr_en

. Rd_en (~slwr_o),//input Rd_en

. Dout (USB_TX),//Output [7:0] Dout

. Full,//Output full

. Empty (empty)//output empty

. Almost_empty (empty)

);

Endmodule

The above design is the key to the state machine design

READ1: This state a clock cycle is used to switch the port direction and switch the cy7c68013a port to EP6 so that the FPGA can read the CY7C68013A data.

READ2: The data port and the CY7C68013A port have switched to EP6, and when the flaga_i indicates that the FIFO is non-empty, there is data to begin reading the data to the FIFO of the FPGA. When reading 512 data, switch to the write state machine

WRITE1: This state a clock cycle is used to switch the port direction and switch the cy7c68013a port to EP2 so that the FPGA can write data to the cy7c68013a.

WRITE2: As long as the FPGA FIFO has data, put the EP2 port to write data, such a write to the btytes just read the data.

11.7 chipcope Logic Analyzer online Commissioning

Set up the Chipscope environment, where we grab signal slwr,slrd,flaga,flagd,usb_tx signal, select the continuous trigger mode, SLWR rising edge trigger, send data from the host computer, pre-send a few ABCD, and then send a single byte A, The signals captured from the Chipscope, as shown, are consistent with the sending data.

11.8 test Results

After the USB firmware has been downloaded, after power-down, the Cyconsole executes the file, you can see that the firmware has been downloaded. Select the endpoint 2OUT channel, using bulk trans can be seen, has been able to write bytes to 68013, select Breakpoint 6IN channel, but unable to read the bytes just sent. After the power-off reboot, download the FPGA corresponding to the slave FIFO transfer mode for the compiled file. After selecting the endpoint 2OUT channel, send 512 bytes of a character, send several times, then select the 6IN channel, read the character a that just sent out. It can be seen that the slave FIFO callback data is normal. The transfer results are as follows:

11.9 Summary

The Slave FIFO is a very important example for USB68013 applications. It realizes the loop transmission of data from PC to Development Board and Development Board to PC. For the transmission of large data, the slave FIFO can guarantee the data without loss while satisfying high efficiency transmission, and it is the most widely used transmission mode in 68013. Beginners can first learn from this example, after understanding the transfer mode, the subsequent more complex transmission mode.

MiS603 Development Board Chapter 11th CY7C68013A Slave FIFO return transmission