MIS603 Development Board Chapter III design of multi-channel crossover device

MiS603 Development Team

Date: 20150911

Company: Nanjing mi Lian Electronic Technology Co., Ltd.

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MIS603 Development Board Chapter III design of multi-channel crossover device

Design idea: Using the logic unit inside the FPGA to count the 50MHZ high frequency clock signal of FPGA input, get the clock of 2, 3, 4, 8 and frequency 1HZ. In order to make the chipscope signal capture, can effectively detect the edge, 3-way is on the basis of 2, using a 2-frequency clock to further design. Specific design process reference.

3.1 Hardware Analysis

The FPGA inputs the global clock 50MHZ, defines the appropriate frequency divider counter, obtains the corresponding clock. Through the Chipscope to capture 2-, 3-, 4-and 8-way results, through the board LED lights, to display the 1HZ clock. The overall design diagram is shown below.

3.2 Timing Design

? Defines the register Div2_o_r, detects the rising edge of the input clock, reverses each rise along the register Div2_o_r, and achieves a 2-way crossover.

? Define register pos_cnt[1:0],neg[1:0], detect the rising and falling edges of the div2_o_r respectively, and when the rising and falling edges are detected, two registers accumulate respectively. Registers are zeroed when counting to 2 ' D2. Another two div3_o_r0 and DIV3_O_R1 are defined, and when two counters are less than 2 ' D1, both Div3_o_r0 and DIV3_O_R1 are assigned a value of 1 and others are assigned a value of 0. The result of the combination of div3_o_r0 and DIV3_O_R1 logic phase or the Div2_o_r further 3.

? Defines a register with a bit width of 2 div_cnt[1:0], detects the input clock rising edge, div_cnt==2 ' b00 or 2 ' b01,4 divider output Register Div4_o_r inversion, div_cnt==2 ' b00, 8-Way output register Div8_o_r reversal.

? Since the input clock 50MHZ, in order to get 1HZ clock, need to define the counter at least 50000000/1=50000000. A 26-bit wide div1hz_cnt counter is defined here. When the input clock rising edge is detected, div1hz_cnt==26 ' d24_999999 or div1hz_cnt==26 ' d49_999999, the 1HZ output register is Div1hz_o_r reversed.

? The timing diagram with the Timedesigner design is shown below. You can write Verilog code based on a time series diagram.

3.3 Program Source code

' Timescale 1ns/1ps

//-----------------------------------------------------------------------------------------------------

/*

* File name: water_lights

* Program Description:

Author

* Date Modified:

* Version number:

* All rights reserved: Nanjing mi Lian Electronic Technology Co., Ltd.

*/

//-----------------------------------------------------------------------------------------------------

Module Water_lights (

Input clk_i,

Input Rst_n_i,

Output [7:0] Led_o

);

1s counting parameters

Parameter hold_1s=26 ' d49_999999; For project

Parameter hold_1s=26 ' D49; For simulation

reg [25:0] div_cnt;

reg [7:0] led_o_r;

[Email protected] (Posedge clk_i or Negedge rst_n_i)

Begin

if (!rst_n_i)

div_cnt<=0;

else if (div_cnt==hold_1s)

div_cnt<=0;

Else

Div_cnt<=div_cnt+1 ' B1;

End

LED light is initialized to 8 ' h01, 1 cycles per second

[Email protected] (Posedge clk_i or Negedge rst_n_i)

Begin

if (!rst_n_i)

Led_o_r<=8 ' h01;

else if (div_cnt==hold_1s)

led_o_r<=led_o_r<<1;

else if (led_o_r==8 ' h00)

Led_o_r<=8 ' h01;

Else

led_o_r<=led_o_r;

End

Assign Led_o=~led_o_r;

Endmodule

3.4 Pre-integrated wiring simulation timing

According to RTL code, the Testbench is designed to simulate the function of multi-channel divider. The simulation diagram is shown below. As can be seen, Div2_o is the Clk_i 2, Div3_o is div2_o three-way, Div4_o, Div8_o are 4 and 8 divided respectively. Div1hz_o because the crossover count is too large to be reflected in the Modelsim, it will be shown through the subsequent LEDs.

3.5 Chipscope on-line Logic Analyzer simulation

The logic Analyzer is set up and the signal to be captured is div2_o_r,div3_o_r,div3_o_r0,div3_o_r1,div4_o_r,div8_o_r. The chipscope captures the signal as shown. Compared with the Modelsim simulation, it can be seen that the requirements of the design to meet.

3.6 Output Results

Download the program to the board to see the core board LED lights flashing 1 times per second, in line with the design of the 1Hz frequency. The other LED lights on the core board are still high in frequency and remain highlighted and cannot be identified by the naked eye.

3.7 Summary

Counting division is one of the simplest examples of Verilog learning, but its importance is self-evident. Many subsequent designs have to use a variety of counting dividers to get the frequency we want.

MIS603 Development Board Chapter III design of multi-channel crossover device