MIS603 Development Board Chapter eighth Ip-core FIFO

MiS603 Development Team

Date: 20150911

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MIS603 Development Board Chapter eighth Ip-core FIFO

FIFO is a kind of resource that FPGA is very important in data stream processing. FIFO can be cached with data, data first in first out. This chapter briefly introduces the use of FIFO, through the UART through the PC to send the data to the FIFO,FIFO cache and back to the computer via the UART, so that the reader has a global understanding. When specific projects, can be used flexibly according to the requirements of the project.

8.1 Adding a FIFO IP CORE

STEP1: New Project Fifo_test

STEP2: Add FIFO IP CORE

STEP3: If you choose, click Next

STEP3: Clock selection-independent clocks (read and write each with a clock), Memory type selection: Blcok RAM

STEP4: Set the read mode to First-word Fall Through, in which the data and read requests are synchronized, if the standard FIFO data is selected for output after the read request. Width of data Select 8bit Depth Selection 32

STEP6:

Almost full flag: Close-up sign, pre-judgment FIFO imminent full flag

Almost full empty: close to NULL flag can be used to pre-determine FIFO impending empty flag bit

Write acknowledge: Writes success response flag bit

Overflow flag: Write overflow flag bit

Valid flag: Read valid flag bit

Underflow flag: Read Overflow flag

STEP7: The synchronous reset mode, the other can be programmed full, and programmable empty flag is not selected

STEP8: Tick The counter, these read and write counters can be used to evaluate the approximate number of FIFO data

STEP9: Click IP for Generate product FIFO

STEP11: Add FIFO IP to the project, and add UART serial port driver, using serial port transmission function to verify the correctness of the project.

8.2 Program Analysis

Readers note that this chapter UART serial driver uses a lite version, and the previous version of the learning function. The lite version is easier to use.

Module Fifo_test (

Input clk_50mhz_i,

Input Rst_n_i,

Input uart_rx_i,

Output Uart_tx_o

);

Parameter write_fifo=0;

Parameter read_fifo=1;

Wire isrxddone,uartisfull;

Wire fifo_full;

Wire Fifo_empty;

Wire [7:0] Fifo_din;

Wire [7:0] fifo_dout;

Wire fifo_wr_en;

Wire fifo_rd_en;

Reg Uartissta;

(*keep = "TRUE" *) wire [4:0]fifo_rd_cnt;

(*keep = "TRUE" *) wire [4:0]fifo_wr_cnt;

Read-write FIFO state machine, start output every time the data reads more than 15

Reg f_s;

Always @ (Posedge clk_50mhz_i) begin

if (~rst_n_i) begin

f_s <= 1 ' b0;

End

ELSE begin

Case (f_s)

Write_fifo:begin

if (fifo_wr_cnt>=5 ' D15) begin//greater than 15 enter Send status

f_s <= Read_fifo;

End

End

Read_fifo:begin

if (Fifo_empty) begin//when FIFO is read empty, enters FIFO write state

f_s <= Write_fifo;

End

End

Endcase

End

End

Assign fifo_wr_en = (~fifo_full) &isrxddone;//Enable write

Assign fifo_rd_en = Uartissta; Enable to read

FIFO Fifo_0 (

. RST (~rst_n_i),//Input RST

. WR_CLK (Clk_50mhz_i),//input WR_CLK

. RD_CLK (Clk_50mhz_i),//input RD_CLK

. DIN (Fifo_din),//input [7:0] Din

. Wr_en (Fifo_wr_en),//input Wr_en

. Rd_en (Fifo_rd_en),//input Rd_en

. Dout (Fifo_dout),//Output [7:0] Dout

. Full (Fifo_full),//Output full

. Almost_empty (Fifo_empty),

. Empty (Fifo_empty),//Output empty

. Rd_data_count (FIFO_RD_CNT),//Output [4:0] Rd_data_count

. Wr_data_count (fifo_wr_cnt)//Output [4:0] Wr_data_count

);

Control the serial port and read data from FIFO

Always @ (Posedge clk_50mhz_i) begin

if (~rst_n_i) begin

Uartissta <= 1 ' b0;

End

ELSE begin

if ((F_s==read_fifo) & (~fifo_empty) & (~uartisfull))

Uartissta <= ~uartissta;

else Uartissta <= 1 ' b0;

End

End

Uartrxd U1 (. Clk_i (Clk_50mhz_i),. Revd (Fifo_din),. IsDone (Isrxddone),. Rxd_i (uart_rx_i));//recieve

Uarttxd U2 (. Clk_i (Clk_50mhz_i),. Issta (Uartissta),. Isfull (Uartisfull),. SENDD (Fifo_dout),. Txd_o (uart_tx_o)); Send

Endmodule

The above program state machine, when the FIFO data is more than 15 start to enter the sending State, in the sending State, as long as the FIFO has data, has been sent until the FIFO data are all sent out. This usage applies to data-volume transmissions, such as video streaming.

8.3 Test Results

As can be seen, each send 32 of their own data, the implementation of a return, one-time 32 bytes of data all back.

8.4 Summary

In this chapter, through a FIFO callback experiment, the data from the PC to enter the Mis603 board, and then saved to the FIFO, when the FIFO data is greater than certain data, then into the module.

MIS603 Development Board Chapter eighth Ip-core FIFO