Modeling and configuration of DSP System

Modeling and configuration of DSP System

[Date: 2008-6-2]

Source: electronic design application by Eyal Bergman

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Embedded software development requires a thorough understanding of the target architecture and its application. It takes a series of steps to transform the concept of an embedded system into an efficient solution that can be effectively deployed in a hardware environment. The entire process includes analysis, architecture setup, evaluation, hardware support, design, coding, debugging, integration, verification, and validation. In this process, if the hardware resources are not effectively utilized or the software is not optimized for the hardware resources, the performance may be seriously affected.

The innovative architecture adopted in the CEVA-X series DSP kernel requires completely novel solutions to take full advantage of possible design variables to control overall performance. CEVA-X1620 is the first product in the CEVA-X kernel series, with a very advanced parallel architecture that can execute up to 8 instructions per machine cycle. For such advanced architectures, it is very important to use hardware resources efficiently and efficiently.

In addition, the CEVA-X integrates the complete memory subsystem, responsible for hierarchical memory management. This includes direct storage access (DMA) controller, on-board cache, write buffer, internal and external memory, memory management and arbitration. With this wide set of functions, you can easily optimize software applications through a complete and accurate simulation environment and advanced configuration capabilities.

Requirements for the simulation environment

For DSP/real-time software development, the simulation environment is very important and must have the following features.

Visibility

Transparency-monitors the work of internal hardware and hardware logic. Even if they are not part of hardware interfaces, they are generally invisible in the actual hardware environment, but understanding them is the key to solving problems and improving performance.

Debugging-in the absence of a precise simulation environment, running all processes on hardware that only provides limited visibility means that more resources are needed and debugging time is increased. Therefore, the simulation environment should provide additional debugging functions not supported by the hardware itself.

Flexibility-This refers to the ability to check the layout of several different systems before being submitted to the final system architecture. To achieve the best performance, we usually need to set different hardware environment parameters and use the software for repeated tests. The simulation environment is required to accurately predict the impact of the selected settings on the system.

Time-parallel hardware and software development can be achieved without too much time and additional special hardware before all running time tests can be performed.

Precise simulation and comprehensive Configuration

The advanced simulation and configuration environment fully adopts Software Modeling and has a wide range of configuration capabilities, which can help system architects and DSP software engineers to better design applications. This method and environment significantly improve system performance and reduce development time accordingly. A comprehensive modeling environment means that the CEVA-X1620 implementation solution can be used in multiple modes for different development stages or different development purposes.

Simulation

The tool first supports the basic instruction set simulation (ISS) mode similar to the standard simulation solution. In this mode, each instruction is executed as an inseparable stage. This mode is fast for software development.

Periodic precision simulation (CAS) is a more advanced simulation mode. In this mode, all pipeline-level architecture behaviors are fully simulated. This mode is very important for the whole system simulation during precision check or hardware verification. In this case, the simulator can be used as the kernel module to conveniently simulate the real hardware functions. In addition to the periodic precision capability, all memory subsystems (MSS) are modeled to simulate the entire system. In this way, the interaction between software and hardware enables real and accurate simulation. This mode includes all MSS modules, so you can debug all storage layers, including cache, write buffer, and internal/external memory. In addition, it can also simulate and analyze different memory la s to observe the access and conflict of memory during Algorithm Execution for each layout.

Configuration

In addition to comprehensive simulation capabilities, CEVA also provides C-level applications and memory configurators. This configurator can automatically analyze the entire simulation environment.

It provides full C-level configuration in basic ISS mode. By finding potential problems, such as application kernels, bottlenecks, and the most code-consuming parts, you can effectively improve software performance. This is a powerful tool that can reduce the number of clock and the code size of non-key features. The application configuration is automatically executed on the C function, without modifying any code. It can also be used in Assembler programs.

Then, application configurations can be executed based on CAS and MSS simulators to obtain its real application performance based on the storage ing and storage conflicts of each function.

After the application is configured in CAS and MSS modes and related functions are determined, the configurator can provide complete memory usage information, this includes Cache Usage and conflict, Summary of every function, code storage, data storage, code storage, and data storage conflicts. This comprehensive and thorough MSS configuration information can guide you to optimize storage for each specific function in the application.

Conclusion

At present, this modeling and configuration process has been successfully used to streamline the number of code for certain Algorithm functions, and has helped many chipsets that use the CEVA kernel for final design to achieve outstanding performance.