Modeling of Verilog HDL

September 13, 2016
Author: dengshuai_super
Source: http://blog.csdn.net/dengshuai_super/article/details/52535925
Disclaimer: Please specify the author and source of the reprint. Modeling Method: Abstract Level

When used in modeling, HDL languages can be categorized according to an abstract hierarchy:
Requirements and concepts can be described at a high level (System level)
The concept of requirements can be described in mathematical form (algorithmic level)
You can use the transfer operation of the Universal Register (RTL) (The code we describe in language can be attributed to the transfer operation of the Register)
You can turn the model described by the General register into a model described by a logic gate (gate-level)
The model described by the logic gate can be transformed into a model described by a circuit switch (switch-level)
Modeling mode : Three ways to model

HDL modeling, in addition to different levels of abstraction can be classified, but also according to its description of the signal is divided into the following three kinds of ways:
1. Data stream Modeling
2. Behavioral Modeling
3. Structured modeling
A description of a signal resource allocation (or a combination of logical connections) in a module becomes a data flow description (Data-flow Description), or data flow modeling (Data-flow Modeling)
A description of the behavior of the signal in the module, called the Behavior description (behavioral Description), or behavior modeling (behavioral Modeling)
Organize many modules into a larger module, described as a structured description (Structural Description), or structured modeling (Structural Modeling)

Example: Two Select a multiplexer
1. Data stream Modeling

Verilog Data Flow modeling for two-selector multiplexer
module two_to_one_dataflow (a,b,s,f);
    Input A;
    Input B;
    input S;
    Output F;

    Assign F = (a&~s) | (b&s);//The Equals sign here is a blocking assignment
Endmodule

' Timescale 1ns/1ns

module TWO_TO_ONE_DATAFLOW_TB;
    Reg A,b,s;
    Wire F;

    Two_to_one_dataflow U1 (. A (a),. B (b),. s (s),. f (f));

    Initial
    begin
        A = 0; b = 0; s =0;
        Forever
        begin
            #20 a = 0; b = 0; s =0
            ; #20 a = 1; b = 0; s =0;
            #20 a = 0; b = 1; s =0;
            #20 a = 1; b = 1; s =0;
            #20 a = 0; b = 0; s =1;
            #20 a = 1; b = 0; s =1;
            #20 a = 0; b = 1; s =1;
            #20 a = 1; b = 1; s =1;
        End
    End
Endmodule

2. Behavioral Modeling

//Behavior Modeling Module two_to_one_behaviour (A,B,S,F);
    Input A;
    Input B;
    input S;
    Output F; When Reg f;//is declared as Register Reg, when it is declared as a wire mesh, by default it is declared as a line//behavior statement, indicating what he is going to do, always followed by a signal sensitive table always @ (a,b,s)//always language A sentence is called a behavior description statement, and the driving signal of a behavior description statement must be declared as Reg begin F <= (A&~s) | (b&s)///non-blocking assignment end Endmodule//explicit modeling and implicit modeling relationships//Explicit modelling (EM): When we want to build a model, we build either the data stream or the name of the name port of the module that is the behavior, explicit modeling//IT
The direction of the port is explicitly declared. implicit modeling (IM): The referenced signal is its input, and the signal being driven is its output (the above always statement is IM) 

' Timescale 1ns/1ns

module TWO_TO_ONE_BEHAVIOUR_TB;
    Reg A,b,s;
    Wire F;

    Two_to_one_behaviour U1 (. A (a),. B (b),. s (s),. f (f));

    Initial
    begin
        A = 0; b = 0; s =0;
        Forever
        begin
            #20 a = 0; b = 0; s =0
            ; #20 a = 1; b = 0; s =0;
            #20 a = 0; b = 1; s =0;
            #20 a = 1; b = 1; s =0;
            #20 a = 0; b = 0; s =1;
            #20 a = 1; b = 0; s =1;
            #20 a = 0; b = 1; s =1;
            #20 a = 1; b = 1; s =1;
        End
    End
Endmodule

3. Structured modeling

Module And_gate_behaviour (a,b,f);
    Input  A;
    Input B;
    Output F;

    Reg F;
    Always @ (A, b)
    begin
        F <= (a&b);
    End
    //and (f,a,b);
Endmodule

Module Or_gate_behaviour (a,b,f);
    Input  A;
    Input B;
    Output F;

    Reg F;
    Always @ (A, b)
    begin
        F <= (a|b);
    End
   //or (F,A,B);

Endmodule

Module Inverter_behaviour (a,f);
    Input  A;
    Output F;
    Reg F;

    Always @ (a)
    begin
        F <= ~a;
    End


Endmodule

Module two_to_one_structural (a,b,s,f);
    Input A;
    Input B;
    input S;
    Output F;

    Wire x1,x2,x3;

    Inverter_behaviour U1 (. A (s),. f (x1));
    And_gate_behaviour U2 (. A (a),. B (s),. F (x3));
    And_gate_behaviour U3 (. A (b),. B (X1),. f (x2));
    Or_gate_behaviour  U4 (. A (x3),. B (x2),. f (f));
Endmodule

' Timescale 1ns/1ns

module TWO_TO_ONE_STRUCTURAL_TB;
    Reg A,b,s;
    Wire F;

    Two_to_one_structural U1 (. A (a),. B (b),. s (s),. f (f));

    Initial
    begin
        A = 0; b = 0; s =0;
        Forever
        begin
            #20 a = 0; b = 0; s =0
            ; #20 a = 1; b = 0; s =0;
            #20 a = 0; b = 1; s =0;
            #20 a = 1; b = 1; s =0;
            #20 a = 0; b = 0; s =1;
            #20 a = 1; b = 0; s =1;
            #20 a = 0; b = 1; s =1;
            #20 a = 1; b = 1; s =1;
        End
    End
Endmodule

Source:
https://ke.qq.com/user/tasks/index.html?cid=117307#tid=100127911&fr=2