MSP430 library Flash Controller

Generally, flash memory in single chip microcomputer is used for storage.ProgramCodeIs a read-only memory. In the MSP430 microcontroller, you can use the built-in flash controller to erase or rewrite any segment of content. In addition, the MSP430 microcontroller also has a flash area (information memory) for storing data that needs to be permanently stored after power loss. The Flash Controller of 430 can be used to complete large data records and Save User-Defined parameters after power loss.

1. Hardware introduction:

   To read and write flash data, you must first understand the Memory Organization of MSP430. 430 the memory structure of the single-chip microcomputer adopts the Von noriman structure. Ram and Rom are centrally stored in the same addressing space, and there is no code space or data space.

   Generally, 430 of single-chip computers are uniformly located in the address range of 0 to 64 K. Only a few high-end models can break through 64 K (for example, fg461x series ). The vast majority of MSP430 single-chip processors are located in the 64 kB range. The approximate address encoding method is as follows:

   This is the memory distribution diagram of msp430f425. The addressing method of other single-chip microcomputer memory in the 64 K range is similar to this: the lower 256b is the register area, followed by Ram; blank; from 1000h to 10ffh is the information flash area; from 0ffffh to 1100h-0ffh is the main memory area (from 0ffffh to the low address, there is a single-chip main flash, the remaining part of the blank ).

   Flash distribution of msp430f14x:

    

   Flash distribution of msp430f16x:

    

   The main flash part and the information flash part are as follows (60 kb flash corresponding single-chip microcomputer, such as msp430f149 and msp430f149 ):

   The main flash is divided into 512b segment units, 0 segment is the MCU interrupt vector program entry address, do not erase this segment or rewrite this segment, if you want to erase or rewrite, save the content to Ram or other segments. Avoid writing or erasing the content in each segment of the main flash to avoid unexpected consequences.

   Flash information is divided into two sections: segments A and B, each of which is B. You can save your own content (the main flash can also, but avoid conflicts with the program code area ); here we refer to the two segments of Information flash as infoa (1080h-10ffh) and infob (1000h-10ffh ).

   Flash operations include writing in words or bytes, writing in blocks, erasure in segments, primary flash, and erasure in all. Any flash operation can be run from flash or RAM.

   A Time Series generator is required for flash operations. The flash controller contains a time series generator to generate the required flash clock. The flash clock range must be between 257khz and 476khz. The sequence generator diagram is as follows:

   The time series generator can select aclk, mclk, and smclk as the clock source, and obtain the flash operation clock between 257khz and 476khz by dividing the frequency. If the clock frequency is no longer in this range, unexpected results will be generated.

   Erased: After erasure, the bits in the memory are changed to 1. Each bit in flash can be written to 1 to 0 through programming, but to change from 0 to 1, the erased period must be used. The smallest unit of erasure is segment. There are three erasure modes:

   Meras erase mode0 1 segment erase1 0 mass erase (all main memory segments) 1 erase all flash memory (main and information. segments)
    

   You can useMeras and erase bits are used to set the erasure mode: Segment erasure, primary flash erasure, and all erasure.

   Enable the time series generator and erasure operation for an empty write of the address in the erases segment: Enable the time series generator and erasure operation for empty write. After the empty write, the busy bit increases immediately until the erasure cycle ends. This bit changes to low (0 ).Busy, meras, and erase bits are automatically reset after the erasure period ends. The time of the erasure period is irrelevant to the Flash size to be erased. The time required for each erasure is the same for the msp430f1xx series microcontroller. The erased sequence is as follows:

   When the empty write address is not in the range of the segment address to be erased, the empty write is invalid and is directly ignored. During the erasure period, the disconnection should be closed until the erasure is complete, and the interruption should be re-opened. During the erasure period, the interruption has been set to a flag, and the request will be immediately responded after the disconnection is enabled.

   Erased from FLASH: The erased operation can be started from flash or RAM. When the operation is started from flash, the flash controller controls the operation sequence, and the CPU operation is paused until the erasure ends. After the erasure cycle ends, the CPU continues to run, starting from the instruction after empty writing. When you start the erasure operation from flash, you can erase the segment of the program to be run. If you erase the flash segment of the program to be run, the CPU operation is unpredictable.

   The erased period from flash is as follows:

   The sample assembler in the User Guide is as follows:

    
   ; Segment erase from flash. 514 kHz <smclk <952 kHz; assumes accvie = nmiie = ofie = 0.MoV # wdtpw + wdthold, & wdtctl; Disable wdtDint//; Disable interruptsMoV # fwkey + fssel1 + fn0, & fctl2; Smclk/2MoV # fwkey, & fctl3; Clear lockMoV # fwkey + erase, & fctl1; Enable segment eraseCLR & 0fc10h; Dummy write, erase S1MoV # fwkey + lock, & fctl3; Done, Set lock...; Re-enable wdt?Eint; Enable interrupts
    

   Enable the erasure operation from Ram: any erasure cycle can be started from Ram. In this case, the CPU will not be paused, but will continue to run the next program from Ram. Before the CPU can access any flash Address, check the busy bit to determine that the erasure cycle ends. If busy = 1 is used to access flash, this is an access conflict. accvifg is set, and the erased result is unpredictable.

   When you start the erasure operation from Ram, the process is as follows:

   You need to confirm that flash is not accessed before the erasure, and then do not allow access to flash before the erasure is complete.

    ; Segment erase from Ram. 514 kHz <smclk <952 kHz; assumes accvie = nmiie = ofie = 0. MoV # wdtpw + wdthold, & wdtctl ; Disable wdt Dint ; Disable interrupts L1 bit # Busy, & fctl3 ; Test busy Jnz L1 ; Loop while busy MoV # fwkey + fssel1 + fn0, & fctl2 ; Smclk/2 MoV # fwkey, & fctl3 ; Clear lock MoV # fwkey + erase, & fctl1 ; Enable erase CLR & 0fc10h ; Dummy write, erase S1 L2 bit # Busy, & fctl3 ; Test busy Jnz L2 ; Loop while busy MoV # fwkey + lock, & fctl3 ; Done, Set lock ... ; Re-enable wdt? Eint ; Enable interrupts 

   Write FLASH: The Write mode is determined by the WRT and blkwrt bits:

   Blkwrt WRT write mode0 1 byte/word write1 1 block write
    

   In these two modes, block writing is about twice faster than writing a word or byte, Because voltage changes until block writing is complete before block writing is complete. The same location cannot be written twice or more before the erasure period, otherwise data corruption will occur. During the write operation, the busy bit is set to 1. After the write is completed, busy is automatically cleared. If the write operation is initiated from Ram, when busy is set to 1, the program cannot access flash. Otherwise, access conflicts may occur, and the flash write operation cannot be predicted.

   Word or byte writing: writing a word or byte can be initiated inside Flash or from Ram. If the write operation is started from flash, the time sequence is controlled by flash, and the CPU running is paused before the writing is complete. After the write is complete, the CPU continues to run.

   The operation sequence is as follows:

   If flash writing is started from Ram, the program will continue to run from Ram. Before the CPU accesses flash again, make sure that the busy bit has been cleared. Otherwise, access conflicts may occur.

   In the word or byte writing mode, the internal programming voltage is applicable to the writing of 64 bytes in byte/word mode, the internally-generated programming voltage is appliedto the complete 64-byte block, each time a byte or word is written, for 32 of the35 fftg cycles. with each byte or word write, the amount of time the block issubjected to the programming voltage accumulates. the cumulativeprogramming time, tcpt, must not be exceeded for any block. if the cumulativeprogramming time is met, the block must be erased before should Ming anyfurther writes to any address within the block.
    

   When writing bytes or words from FLASH:

   ; Byte/word write from flash. 514 kHz <smclk <952 kHz; assumes 0ff1eh is already erased; assumes accvie = nmiie = ofie = 0.MoV # wdtpw + wdthold, & wdtctl; Disable wdtDint; Disable interruptsmov # fwkey + fssel1 + fn0, & fctl2; Smclk/2MoV # fwkey, & fctl3; Clear lockMoV # fwkey + WRT, & fctl1; Enable writeMoV #0123 H, & 0ff1eh; 0123 H −> 0ff1ehMoV # fwkey, & fctl1; Done. Clear WRTMoV # fwkey + lock, & fctl3; Set lock...; Re-enable wdt?Eint; Enable interrupts
    

   When the write operation is started from Ram:

    ; Byte/word write from Ram. 514 kHz <smclk <952 kHz; assumes 0ff1eh is already erased; assumes accvie = nmiie = ofie = 0. MoV # wdtpw + wdthold, & wdtctl ; Disable wdt Dint ; Disable interrupts L1 bit # Busy, & fctl3 ; Test busy Jnz L1 ; Loop while busy MoV # fwkey + fssel1 + fn0, & fctl2 ; Smclk/2 MoV # fwkey, & fctl3 ; Clear lock MoV # fwkey + WRT, & fctl1; Enable write MoV #0123 H, & 0ff1eh ; 0123 H −> 0ff1eh L2 bit # Busy, & fctl3 ; Test busy Jnz L2 ; Loop while busy MoV # fwkey, & fctl1 ; Clear WRT MoV # fwkey + lock, & fctl3 ; Set lock ... ; Re-enable wdt? Eint ; Enable interrupts 

   Block write: When writing multiple consecutive words or bytes, block write can improve the flash access speed. During block writing, the internal programming voltage is always present during 64-byte block writing. Block write operations cannot be enabled in flash memory. Block write operations must be initiated from Ram. During block write, the busy bit is set. Wait bit must be detected when writing each byte or word. When the next word or byte can be written, the wait bit is set.

   The block write process is as follows:

    

    ; Write one block starting at 0f000h.; must be executed from Ram, assumes flash is already erased.; 514 kHz <smclk <952 kHz; assumes accvie = nmiie = ofie = 0. MoV #32, R5 ; Use as write counter MoV # 0f000h, R6 ; Write pointer MoV # wdtpw + wdthold, & wdtctl ; Disable wdt Dint ; Disable interrupts L1 bit # Busy, & fctl3; Test busy Jnz L1; Loop While Busymov # fwkey + fssel1 + fn0, & fctl2 ; Smclk/2 MoV # fwkey, & fctl3 ; Clear lock MoV # fwkey + blkwrt + WRT, & fctl1 ; Enable block write L2 mov write_value, 0 (R6) ; Write location L3 bit # Wait, & fctl3 ; Test wait JZ L3 ; Loop while wait = 0 INCD R6 ; Point to next word Dec R5; Decrement write counter Jnz L2 ; End of block? MoV # fwkey, & fctl1 ; Clear WRT, blkwrt L4 bit # Busy, & fctl3 ; Test busy Jnz L4 ; Loop while busy MoV # fwkey + lock, & fctl3 ; Set lock ... ; Re-enable wdt if needed Eint ; Enable interrupts 

   When any write or erase operation is started from ram, and busy = 1, the CPU cannot read or write or from any flash location. Otherwise, access conflicts occur and the accvifg settings make the results unpredictable. In addition, if the flash write causes WRT = 0 and accvifg to interrupt the flag settings, flash will not be affected.

   If the write or erase operation is started from flash, when the CPU accesses the next instruction (read instruction from flash), The Flash Controller returns 03fffh to the CPU; 03fffh is the instruction jmp pc, this keeps the CPU running until the flash operation is complete. After the flash write or erase operation is complete, the CPU can continue to access the subsequent commands.

   When busy = 1, flash access:

   Before starting the flash operation, you must stop all interrupt sources. If there is an interrupt response during the flash operation, when reading the address of the interrupt service program, 03fffh will be received as the address of the interrupt service program. If busy = 1, the CPU will always execute difficult imp PC commands; after flash operations are completed, the interrupted service program will be executed from 03fffh instead of the correct address of the interrupted program.

   Stop write or erase: Any write or erase operation can exit emex by setting an emergency exit bit before the operation is completed normally. When emex is set, the current active operation is immediately stopped and the flash controller is stopped. All flash operations are stopped and the Read mode is returned. All bits of fctl1 are reset. The operation results are unpredictable.

   Set and access the Flash Controller: fctlx is a 16-bit, password-protected, read-write register. To write these registers, the password 0a5h must be included at a high level. If it is not 0a5h, it will cause a reset. When reading a register, the high bit reads 96 h.

   When the fctl1 register is erased or written to a word or byte, access conflict will occur. when the block is written, you can write the fctl1 register when wait = 1. When the wait = 0, write the fctl1 register as an access conflict and set it to accvifg. When busy is set to 1, access conflicts occur in all the written fctl2 registers. When busy = 1, all fctlx can be read without causing access conflict.

   Flash interrupt: The Flash Controller has two interrupt sources: keyv and accvifg. Accvifg is set when access conflicts occur. When the accvifg is re-enabled after the flash operation is complete, the request will be interrupted. The accifg and NMI are the same interrupt vectors, so the interrupt does not need to be allowed by the GIE bit to generate the interrupt request. The accvifg bit must be detected by the software to identify an access conflict. The accvifg bit must be reset by the software. Keyv is a key value error. It is set when the flash register is not written with the correct high-level password, which immediately causes the PUC signal to reset the entire hardware.

   Programming Flash hardware: programming 430 Flash content has three options, through JTAG, through BSL and user customization. You can use a single-chip microcomputer program to access your flash.

   The Flash register list is as follows:

    
   Register short form register type address initial stateflash memory control register 1 fctl1 read/write 0128 H 09600 h with pucflash memory control register 2 fctl2 read/write 012ah 09642 h with pucflash memory control register 3 fctl3 read/write 012ch 09618 h with pucinterrupt enable 1 ie1 read/write 000 h reset with pUC
    

   Flash hardware has been introduced so much. For more information, see the User Guide provided by TI.

2. Program Implementation:

   First, set the flash clock to initialize the flash controller:

    
   VoidFlashinit () {fctl2 = fwkey + fssel_2 + fn1;// Smclk/3 = 333 kHz by default}
    

   This function only sets the clock.

   Erasure function:

   VoidFlasherase (Unsigned intADDR ){Char* Flashptr; flashptr = (Char*) ADDR; fctl1 = fwkey + erase;// Set erase bitFctl3 = fwkey;// Clear lock bitDint; * flashptr = 0;// Dummy write to erase flash segment BWaitforenable ();// BusyEint; fctl1 = fwkey;// LockFctl3 = fwkey + lock;// Set lock bit}
    

   Like the preceding process, the parameter is the first address of the segment to be erased. The waitforenable function waits for the busy flag to return to zero to complete the operation.

   VoidWaitforenable (){While(Fctl3 & busy) = busy );// Busy}
    

   Write Bytes:

   VoidFlashwritechar (Unsigned intADDR,CharData ){Char* Flashptr = (Char*) ADDR;// Segment a pointerFctl1 = fwkey + WRT;// Set WRT bit for write operationFctl3 = fwkey;// Clear lock bitDint; * flashptr = data;// Save dataWaitforenable ();// BusyEint; fctl1 = fwkey;// Clear WRT bitFctl3 = fwkey + lock;// Set lock bit}
    

   Write word:

   VoidFlashwriteword (Unsigned intADDR,Unsigned intData ){Unsigned int* Flashptr = (Unsigned int*) ADDR; fctl1 = fwkey + WRT;// Set WRT bit for write operationFctl3 = fwkey;// Clear lock bitDint; * flashptr = data;// Save dataWaitforenable ();// BusyEint; fctl1 = fwkey;// Clear WRT bitFctl3 = fwkey + lock;// Set lock bit}
    

   The difference between writing a word or byte function is that the pointer type is different.

   Read words or Bytes:

    
   CharFlashreadchar (Unsigned intADDR ){CharData;Char* Flashptr = (Char*) ADDR; Data = * flashptr;Return(Data );}Unsigned intFlashreadword (Unsigned intADDR ){Unsigned intData;Unsigned int* Flashptr = (Unsigned int*) ADDR; Data = * flashptr;Return(Data );}
    

   The difference between the two functions is that only the pointer type is different.

   These functions are the same as the procedures described in the previous hardware section.

3. Example:

   In the same way as before, add the c file to the project,Source codeThe file contains an H file, which can be used. For details, refer to the example project:

   The main program of the demo is as follows:

    
   # Include<Rjx16x. h># Include"Flash. H"IntA;VoidMain (Void){// Stop watchdog timer to prevent time out ResetWdtctl = wdtpw + wdthold; clkinit (); flashinit (); flashwritechar (infob, 0x25); A = flashreadchar (infob );// Infob has a macro definition in the H fileFlashwriteword (infob + 2, 0x5669); A = flashreadword (infob + 2); flasherase (infob); lpm0 ;}
    

   Write Data to the first address of infob (1000 h). Write one byte before writing one word. (Note that when writing a word, it must be an even address, an odd address is written in the first even address of the address.) read the address and erase it. The programs here are all run in flash, and the programs running in RAM are not demonstrated. If you run a program in Ram, you need to first move the program from flash to ram, and then jump to ram to run.

   Debugging is as follows:

   During debugging, the view-memory menu calls up the memory window and observes the Flash content.

   The info flash part is written here. The result of observing this part is the same as that of writing.

The Flash program controller program is here. Flash can be used to store long-term data. Are you welcome to discuss any shortcomings.

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