My FPGA learning process (--PWM) pulse width modulation

PWM is a technology to regulate the output power (commonly known as voltage regulation), the principle is to change the duty ratio of the output square wave, the specific output see:

The output signal is the voltage value, when the load is constant resistance, the output power is 25%, 50%, 75%, respectively.

The implementation method is as follows:

• Set up a counter in which the first line is a 4-bit counter that automatically changes to 0 per 15. Then you can get the output frequency equal to 1/16 of the clock.

• When the value of the counter is less than a certain value, the output is 0, which is higher than or equal to a value of 1.

Assuming that the control is a small lamp for 1/8 power output, then we need a value of (4 ' HD), when the counter is less than or equal to 13 output 0, otherwise output 1.

The specific code is as follows:

If the clock is 50MHz, a clock period of 2ns, according to the calculation can be obtained above the PWM output signal period of NS, frequency about 1.5MHz. Since the 1.5MHz frequency far exceeds the human eye 100Hz resolution limit, so in people's opinion LED will always glow but low brightness.

Not all peripherals, however, can withstand frequencies as high as 1.5MHz. Many devices contain transistors, but the transistor is a cutoff frequency limit problem, when the output pin through the transistor to amplify the output current, the high frequency will cause the output to fail, so in most cases we need to reduce the PWM output frequency.

        An arbitrary integer divider can be obtained using the ring counter, which has been tried in the electronic clock. We can use the output of the crossover module as the clock input for another circuit, but the clock signal generated by this method is not stable enough. The phase-locked loop can perform arbitrary proportional crossover, octave, and shift operation on the clock signal. The PLL is divided into digital (DLL) and Analog (PLL) two, Altera company in FPGA integrated analog phase-locked loop, Xilinx Company's device integration of both analog and useful digital.

The clocks available inside the FPGA are very limited compared to the free wiring of ASICS. The clock available to the FPGA involves the problem of the global clock network. As this does not involve the problem of the artboard, for the clock network is not more than a repeat.

How to use the phase-locked loop:

        First locate and open the Megawizard plug-in Manager in the Tools menu bar and follow the steps below to configure the use of the PLL IP core

This IP core outputs up to 5 signals, since we only need one output C0, so C1 ~ C4 is set to default (not turned on).

In this case, the PLL core is configured, the schematic connection method:

The clock in this paper is 50MHz, and the output frequency can be calculated.

50M = 50_000_000–> 50_000_000/25_000 = 2000–> 2000/16 = 125

If you feel that the effect is not obvious enough to add a full-bright lamp in the PWM code as a reference, you can also change the duty to 4 ' HE (1/16 Power), the reader can also try to increase the frequency divider in the PLL to let the light flashing (as long as the phase-locked loop configuration occurs able to implement the requ The ested PLL indicates that the configuration is feasible). A period of 125Hz is 0.008s = 0ms = 8_000 us, using the graphical emulation input to verify is obviously not very realistic, in addition we used the IP core in the project, in the next I will describe how to simulate the project with IP core.

My FPGA learning process (--PWM) pulse width modulation