Network Port Literacy III: The relationship between Mac and PHY for Ethernet chips

Q: How do I implement a monolithic Ethernet microcontroller?

A: The trick is to integrate microcontrollers, Ethernet media access controllers (Macs) and physical interface transceivers (PHY) into the same chip, which removes many external components. This scheme enables MAC and PHY to be well matched, while reducing the number of kohiki feet, Reduce the chip area. The monolithic Ethernet microcontroller also reduces power consumption, especially in the case of a power-down mode.

Q: What is an Ethernet Mac?

A: The MAC is media access control, which is the sub-layer protocol for the medium-to-child. The protocol is located in the lower half of the data link layer in the OSI Seven layer protocol, and is primarily responsible for controlling and connecting physical media to physical layers. When sending data, the MAC protocol can determine in advance whether the data can be sent, If it is possible to send the data with some control information, and eventually send the data and control information in the specified format to the physical layer, when the data is received, the MAC protocol first to determine the input information and whether there is a transmission error, if there is no error, The control information is sent to the LLC layer. The layer protocol is an Ethernet Mac defined by the IEEE-802.3 Ethernet standard. The latest Mac supports both 10Mbps and 100Mbps speeds of two.

The Ethernet Data Link layer actually contains the MAC (media access control) Sublayer and the LLC (Logical link Control) sublayer. A piece of Ethernet card the function of Mac chip not only realizes the function of the Mac Sublayer and the LLC Sublayer, but also provides the standard PCI interface to realize the data exchange with the host.

After the MAC receives the IP packet (or packets from the other Network layer protocol) from the PCI bus, it splits and re-packs the frame to a maximum of 1518Byte and a minimum of 64Byte. This frame includes the destination MAC address, its own source MAC address, and the protocol type in the packet ( For example, the type of IP packet is represented by 80). Finally there is a DWORD (4Byte) CRC code.

But where does the target MAC address come from? This involves an ARP protocol (a protocol between the network layer and the data Link layer). The first time a destination IP address is transmitted, an ARP packet is emitted, and the target address of the MAC is the broadcast address, which says: " Who is xxx.xxx.xxx.xxx the owner of this IP address? "Because it is a broadcast packet, all hosts on this LAN receive this ARP request." The host receiving the request compares this IP address to its own, and if it is not the same, the ARP response packet is issued if it is the same. The host of this IP address receives the ARP Request packet and replies to the ARP response saying: " I am the owner of this IP address. This package includes his MAC address. The destination MAC address of the frame to which the IP address is given is determined. (Other protocols such as Ipx/spx also have a corresponding protocol to complete these operations.)

The association between the IP address and the MAC address is stored in the host system, called the ARP table, and is completed by the driver and the operating system. In Microsoft's system, you can view the ARP table with the ARP-A command. It is also the same when the data frame is received, after the CRC is done, If there is no CRC validation error, remove the frame head, take the packet out through the standard excuses passed to the driver and the upper level of the Protocol Inn, and finally the right to reach our application.

There are also control frames, such as flow-control frames, that require the Mac to recognize and perform the corresponding behavior directly.

One end of the Ethernet MAC chip is connected to the computer PCI bus, and the other end is connected to the PHY chip, which is linked through the Mii interface.

Q: What is MII?

A: Mii is the media independent interface, which is the Ethernet industry standard defined by IEEE-802.3. " Media independence "indicates that any type of PHY device can work correctly without the MAC hardware being redesigned or replaced. It includes a data interface and a management interface between Mac and PHY.

• The data interface includes two separate channels for the transmitter and receiver respectively. Each channel has its own data, clock and control signals. The MII data interface requires a total of 16 signals, including TX_ER,TXD<3:0>,TX_EN,TX_CLK, col,rxd<3:0>,rx_ex,rx_clk,crs,rx_ DV and so on. Mii transmits data in two-way with a 4-bit half-byte transmission, with a clock rate of 25MHz. Its operating rate can reach 100mb/s;
• The Mii management interface is a two-signal interface, one is a clock signal and the other is a data signal. PHY can be monitored and controlled by the upper layer through the management interface. Its management is using SMI (Serial Management Interface) The bus is completed by reading and writing to the PHY register. The part registers in the PHY are defined by IEEE so that PHY reflects its current state into the register, and the Mac continuously reads the state register of the PHY via the SMI bus to know the current PHY state, such as the connection speed, The ability to duplex. Of course, you can also set the PHY register through the SMI for control purposes, such as open shutdown of the flow control, self-negotiation mode or mandatory mode. Both the status register and the control register for the physical connection of the Mii bus and the SMI Bus or PHY are IEEE compliant, So the Mac and PHY of different companies can work together as well. Of course, in order to match the different company's own unique features of the PHY, the driver needs to make corresponding changes.

Mii supports 10Mbps and 100Mbps operation, an interface consists of 14 lines, its support is relatively flexible, but there is a disadvantage because it is a port with too many signal lines, if a 8-port switch to use 112 lines, 16 ports will be used to 224 wires, To port 32 will be used to 448 lines, generally in accordance with this interface to do the switch, is not very realistic, so modern switch production will use some other standards from the Mii simplified, such as rmii,smii,gmii.

The rmii is a simplified Mii interface that has a signal line that is less than the Mii interface when it is sent and received, so it is generally required to be a 50MHz bus clock. Rmii is generally used in multiport switches, it is not each port arranged to receive, send two clocks, Instead, all of the data ports have a common clock for all the ports to send and receive, saving a lot of port numbers here. One port on the RMII requires 7 data lines, one times less than Mii, so the switch can access more than one data port. Like Mii, the RMII supports the bus interface speed of 10Mbps and 100Mbps.

Smii is a media interface proposed by Cisco, which has less than rmii number of signal lines, s is the meaning of serial. Because it transmits data with only one signal line, a signal line transmits the data, so in order to meet the demand of 100Mbps bus interface speed, It has a clock frequency of 125MHz, why 125MHz, because the data line inside the transmission of some control information. Smii a port with only 4 signal lines to complete the 100Mbps transmission, compared to the rmii is almost a few times less signal line. SMII support in industry is very high. Similarly, all ports have a common external 125MHz clock for data reception and dispatch.

Gmii is the Mii interface of the gigabit network, which also has a corresponding Rgmii interface, which represents a simplified gmii interface.

MII Bus

The MII bus specified in the IEEE802.3 is a universal bus used to connect different types of PHY to the same network controller (MAC). Network controller can use the same hardware interface with any PHY.

GMII (Gigabit MII)

The GMII uses 8-bit interface data with a working clock of 125MHz, so the transfer rate can be up to 1000Mbps. Compatible with the 10/100 Mbps operating mode as defined by Mii.

The Gmii interface data structure conforms to the IEEE Ethernet standard. The interface definition is shown in IEEE 802.3-2000.

transmitter :

• gtxclk--Gigabit TX.. Signal Clock signal (125MHZ)
• txclk--10/100mbps Signal Clock
• txd[7..0]--is sent data
• txen--transmitter Enable signal
• txer--transmitter error (used to destroy a packet)

Note: At a gigabit rate, a GTXCLK signal is provided to the PHY and the txd,txen,txer signal is synchronized with this clock signal. Otherwise, at 10/100mbps rate, the PHY provides a TXCLK clock signal, and the other signals are synchronized with the signal. The operating frequency is 25MHz (100M network ) or 2.5MHz (10M network).

receiver :

• rxclk--receive clock signal (extracted from received data, therefore not associated with GTXCLK)
• rxd[7..0]--receiving data
• rxdv--receiving data valid indication
• rxer--receiving data error indication
• col--Conflict Detection (only for half-duplex state)

Manage Configurations

• mdc--Configuring Interface Clocks
• mdio--Configuring interface I/O

The Management configuration interface controls the characteristics of the PHY. The interface has 32 register addresses, 16 bits per address. Of these, the first 16 have been specified for use in the IEEE 802.3,2000-22.2.4 Management Functions, while the rest are designated by each device.

RMII (reduced Media independant Interface)
Simplified Media Standalone Interface
is one of the standard Ethernet interfaces and has fewer I/O transmissions than Mii.

Rmii Port is to use two lines to transmit data, the MII port is 4 lines to transmit data, Gmii is 8 lines to transfer data. Mii/rmii is just an interface, for 10Mbps line speed, MII clock rate is 2.5MHz, rmii need 5MHz; For 100Mbps wire speed, the MII requires a clock rate of 25mhz,rmii and 50MHz.

Mii/rmii is used for transmission of Ethernet packets, in the Mii/rmii interface is 4/2bit, in the Ethernet PHY need to do string and conversion, codec and so on to the twisted pair and fiber transmission, its frame format follows IEEE 802.3 (10M)/ieee 802.3u (100M) /ieee 802.1q (VLAN). The format of the Ethernet frame is: Leader + start bit + Destination MAC address + source MAC address + type/length + data +padding (optional) +32BITCRC
If there is a VLAN, then add a 2-byte VLAN tag after the type/length, where 12bit represents the VLAN ID, and 4bit represents the priority of the data!

Q: What is Ethernet PHY?

A: PHY is a physical interface transceiver that implements the physical layer. The IEEE-802.3 standard defines the Ethernet PHY. Includes MII/GMII (media Independent interface) sub-layer, PCS (physical coding sub-layer), PMA (physical media attached) sub-layer, PMD (physical media-related) sub-layer, MDI child layer. It complies with the specifications for 10BaseT (14th) and 100BaseTX (24th and 25th) in ieee-802.3k.

PHY receives data from MAC when it sends data (for PHY, there is no frame concept for it, it is data regardless of address, data or CRC.) for 100BaseTX because of the use of 4b/5b encoding, every 4bit to increase the number of 1bit error detection code), Then the parallel data is converted into serial stream data, and then the data is encoded according to the coding rules of the physical layer, and then the data is sent out by the analog signal. The process of receiving the data in turn. PHY also has an important function of implementing CSMA/CD. It detects if data is being transmitted on the network, If there is data waiting in the transmission, once the network is detected to be idle, wait for a random time to send the data out. If the two happen to send the data at the same time, that will cause conflict, when the conflict detection agencies can detect the conflict, Then each waits for a random time to resend the data. This random time is very fastidious, not a constant, the random time calculated at different times are different, and there are multiple algorithms to cope with the probability of a very low occurrence of the second collision between the two hosts.

Many netizens in the access internt broadband, like to use "grab line" strong network card, is because different PHY collision after the calculation of random time method design, make some network cards compared "take advantage". However, the line is only for the broadcast domain network, For the switching network and ADSL such a point-to-end connection to the local device access method is meaningless. and "Rob Line" is only relative, there will be no qualitative changes.

Nowadays, the popularization of the switch network makes the network of conflict domain much less and greatly improves the bandwidth of the network. However, if the hub, or shared bandwidth to the Internet is a conflict domain network, collision. The biggest difference between a switch and a hub is: One is to build a network-to-point LAN switching device, one is to build a network of conflict domain LAN interconnection devices.

In addition to this, PHY also provides important functions for connecting to the end device and shows the status and working status of the current connection through the LED light. When we give the network card access to the network cable, the PHY constantly sends out pulse signals to detect the device on the end, they communicate through the standard "language", Negotiate with each other but determine the connection speed, duplex mode, whether or not to use flow control. Typically, the negotiated result is the maximum speed and the best duplex mode that can be supported in both devices. This technique is called autonegotiation or nway, they are a meaning – auto-negotiation.

The specific transfer process is, when sending data, the NIC first listens to the media for carrier (the carrier is indicated by voltage), if any, it is believed that other sites are transmitting information, continue to listen to the media. Once the communication medium is quiet within a certain period of time (known as Inter-frame gap ifg=9.6 microseconds), it is not occupied by other sites. The frame data is sent and continues to listen to the communication media to detect the conflict. During data transmission, if a conflict is detected, stop the send immediately and send a "blocking" signal to the media, notifying other sites that a conflict has occurred, discarding the corrupted frame data that may have been received. And wait for a random time (the algorithm that CSMA/CD determines the wait time is the binary exponential backoff algorithm). After waiting for a random amount of time, a new send is sent. If a conflict persists after multiple retransmissions (greater than 16 times), the send is discarded. When received, the NIC browses each frame transmitted on the media, If the length is less than 64 bytes, it is considered a conflict fragment. If the received frame is not a conflict fragment and the destination address is a local address, the integrity check is performed on the frame, if the frame length is greater than 1518 bytes (called an extra-long frame, may be caused by the wrong LAN driver or interference), or fails the CRC check, The frame is considered to be distorted. The frame that is validated is considered valid, and the NIC receives it for local processing.

Q: What are the reasons for the difficulty of integrating Ethernet MAC and PHY monolithic integration?

A: PHY incorporates a large number of analog hardware, and the Mac is a typical all-digital device. The chip area and the analog/digital hybrid architecture are the reasons why the Mac was first integrated into the microcontroller and left the PHY out of the chip. More flexible, denser chip technology already enables single-chip integration of Mac and PHY.

Q: Are there other components required on the NIC besides the RJ-45 interface?

A: PHY and Mac is the main component of the network card, NIC General with RJ-45 socket, 10M network card RJ-45 socket is only used 1,2,3,6 four needles, and 100M or 1000M network card is eight needles are all. In addition, other components are required, Because PHY provides the overwhelming majority of simulation support, in a typical implementation, it is still necessary to add 6, 7 discrete components and a LAN insulation module. The insulating module generally uses a 1:1 transformer. The main function of these components is to protect the PHY from damage caused by electrical errors.

In addition, a CMOS process chip works when the signal level is always greater than 0V (depending on the chip's process and design requirements), but such a signal to 100 meters or even longer places will have a large loss of DC components. And if the external network cable directly connected to the chip, electromagnetic induction (Thunder) and static electricity, it is easy to cause damage to the chip. Then the device grounding method is different, the power grid environment will cause the two sides of the 0V level inconsistency, so that the signal from A to B, because a device of 0V and B point 0V level is not the same, this will lead to a large current from high potential equipment to low potential equipment.

In order to solve the above problem transformer ( isolation transformer ) This device was born. It sends the differential signal of the PHY out to the differential-mode coupled coil-coupled filter to enhance the signal, And it is coupled to the other end of the connection cable by the conversion of the electromagnetic field. This not only makes the network cable and PHY not physically connected to the signal, cut off the DC component of the signal, but also can transfer data in different 0V level devices.

The isolation transformer itself is designed to withstand the 2kv~3kv voltage. It also acts as a protection against lightning (which I personally think is not suitable for lightning strikes). Some friends of the network equipment in the thunderstorm weather is easy to burn, most of the PCB design unreasonable caused by, and most of the equipment to burn the interface, Few chips have been burnt, which is the protective effect of the isolating transformer.

The isolation transformer itself is a passive element, but the PHY signal is coupled to the network cable, and does not play a role in power amplification. So who decides the longest distance of the transmission of a network card signal?

The maximum transmission distance of a net card and the compatibility with the connection to the end device are primarily PHY-determined. However, the output power of the PHY which can send the signal over 100 meters is also relatively large, More prone to EMI problems. This is where the right transformer is needed. The PHY of the eldest company Marvell, often capable of transmitting 180~200 meters, far exceeds the IEEE's 100-metre standard.

The RJ-45 connector realizes the connection between the network card and the network cable. It has 8 pieces of copper which can be connected with 4 pairs of twisted pair (8) wires in the network cable. of which 100M is the transmission of data, the 3,6 is to receive data. Between the two is a pair of differential signals, which means that their waveforms But the phase difference 180 degrees, the same time the voltage amplitude of each other is positive and negative. Such signals can be transmitted farther, strong anti-jamming ability. Similarly, 3,6 is a differential signal.

8 lines in the network cable, each of the two twisted together to become a pair. When we make the network cable, we must pay attention to let in one of the pair, 3,6 in a pair. Otherwise the use of this cable in long-distance situations can lead to the inability to connect or the connection is very unstable.

The new PHY now supports the Auto Mdi-x feature (also requires transformer support). It can achieve the RJ-45 interface of the transmission signal line and 3, 6 The function of the receiving signal line is exchanged automatically. Some PHY even supports the automatic switching of positive and negative signals in a pair of lines. So we don't have to worry about connecting a device with a straight-through cable or a crossover cable. This technology has been widely used in switches and SOHO routers.

In the 1000BASD-T network, one of the most common modes of transmission is the use of all 4 pairs of twisted-pair cables, which increase the 4,5 and 7, 8来 together to transmit the received data. Because the 1000BASED-T network's specifications include Automdi-x functionality, Therefore, they can not strictly determine the relationship between their outgoing or receive, depends on the specific outcome of the negotiations between the two sides.

The main function of a network card is basically the implementation of the above devices.

Other, there is an EEPROM chip, usually a 93c46. It records the vendor ID of the NIC chip, the subsystem vendor ID, the MAC address of the network card, some configuration of the NIC, such as the address of the PHY on the SMI bus, the capacity of the bootrom, Whether to enable Bootrom boot system and so on.

There are bootrom on many network cards. It is used to boot the operating system for diskless workstations. Since there is no disk, some of the necessary programs and protocol stacks are put inside, such as rpl,pxe. In fact, it's a standard PCI Rom. So there will be some hard disk write protection card can be implemented by burning the bootrom of the network card. In fact, the ROM of the PCI device can be placed in the motherboard BIOS. This ROM can be detected as well as the device in the boot computer. AGP is configured in many places like PCI , so many of the video card's BIOS can also be placed in the motherboard BIOS. That's why onboard NICs we've never seen bootrom.

The last part is the power supply. Most network cards now use voltages of 3.3V or less. There are two voltages. Therefore, a power conversion circuit is required.

Moreover, in order to implement the wake on line function, the NIC must ensure that a very small portion of all PHY and Mac is always in a state of power, which requires the conversion of the 5V standby voltage on the motherboard to the circuit of the PHY operating voltage. After the console is powered on, The operating voltage of the PHY should be replaced by a voltage that is transferred from 5V to save the consumption of 5V standby. (many inferior NICs do not).

There is a wake on the line function of the NIC generally also has a WOL interface. That's because PCI2.1 didn't have a PCI device to wake up the host, so a thread was needed to connect to the South Bridge via the Wol interface on the motherboard to realize the WOL function. New motherboard-to-board adapter general support PCI2.2/ 2.3, extended the pme# signal function, do not need that interface and through the PCI bus can realize the wake-up function.

Let's take a look at two graphs.

Mac and PHY separate Ethernet cards

Mac and PHY integrated on one chip Ethernet card

The components are:

①rj-45 interface

②transformer (Isolation transformer)

③phy Chip

④mac Chip

⑤eeprom

⑥bootrom Slots

⑦wol Connector

⑧ Crystal Oscillator

⑨ Voltage Conversion Chip

⑩led indicator

There are two main functions of the network card: one is to encapsulate the computer's data into frames, and send the data to the network via a cable (which is electromagnetic wave to the wireless network), and the second is to receive the frames transmitted by other devices on the network, and to regroup the frames into data and send them to the computer where they are located However, normally only the frames and broadcast frames sent to the computer are accepted, and the remaining frames are discarded. It is then transferred to the system CPU for further processing. When the computer sends the data, the NIC waits for the appropriate time to insert the packet into the data stream. The receiving system notifies the computer that the message is fully reachable, and if there is a problem, The other person will be asked to resend.

Q: Why is the 10BaseT and 100BaseTX PHY implemented differently?

A: The grouping descriptions of the two implementations are essentially the same, but the signaling mechanisms are completely different. The goal is to prevent a hardware implementation from handling two of speeds easily. The 10BaseT uses Manchester code and 100BaseTX uses 4B/5B encoding.

Q: What is Manchester code?

A: Manchester code is also known as Manchester phase encoding, which implements each bit through phase changes (Figure 2). Typically, the rising edge of the middle of a clock cycle represents "1", and the Falling edge represents "0". The phase change at the end of the cycle is negligible, but sometimes it may be necessary to calculate this phase change, This depends on the value of the previous bit.

Q: What is 4b/5b encoding?

A: 4b/5b encoding is a block encoding. It encodes a 4-bit block into a 5-bit block. This causes the 5-bit block to always have at least 2 "1" transformations, so the clock is always synchronized within a 5-bit block. This method requires 25% additional overhead.

Q: What is the relationship between the Mac and PHY of the NIC?

A: The NIC works on the last two layers of the OSI, the physical layer and the data link layer, and the physical layer defines the electrical and optical signals, line States, clock benchmarks, data encoding, and circuitry needed for data transmission and reception, and provides a standard interface to the data link layer device. The physical layer of the chip is called PHY. The data Link layer provides Data frame construction, data error checking, Transmission control, to the network layer to provide standard data interface and other functions. The chip of the data link layer in the Ethernet card is called the Mac controller. These two parts of the NIC are done together. The relationship between them is PCI bus connected to Mac bus, Mac connected phy,phy LAN (also not directly connected, there is a pressure swing device).

How PHY and Mac transmit data and communicate with each other. Standard Mii/gigamii defined by IEEE (Media independed interfade, medium Independent interface) interface to the Mac and PHY. This interface is defined by the IEEE. The Mii interface conveys control over all data and data on the network. The Ethernet interface is essentially the process by which a Mac controls PHY via the Mii bus.

Q: Is the analog or digital signal transmitted on the network cable?

A: It is an analog signal. Because it is transmitted and received is the analog technique used. Although the information it transmits is digital (it is not the signal that is transmitted, it can be called a digital signal).

Simple example: We know that the phone is an analog signal, but when we dial the Internet, the telephone line transmits digital information, but the signal itself is still analog. However, ADSL is also transmitted via telephone lines, but it is a digital signal. This depends on the technology that it transmits and accepts.

Q: If the operating system does not load the network card driver, although the network card in the system device tree, but the interface is not created, the network card can actually receive data?

A: There are many details, I based on the Intel network card spec probably wrote, want to write as much as possible, so there is no intention to use the terminology in spec, in addition, although the article is mac/phy, but the Light Mouth card (SERDES) is similar.

2. PCI devices do reset after entering the d0uninitialized (non-initialized D0 state, refer to the PCI Power Management specification), at this time the NIC Mac and DMA are not working, PHY is working in a special low power state;
4. When the operating system creates the device tree, initializes the device, and the PCI command Register's Memory access enable or the I/O access enable bit will be enabled, which is d0active. At this time the Phy/mac is able;
6. PHY is enabled to receive data on the physical link, otherwise it cannot receive FLP/NLP, and PHY cannot establish a physical connection. But this kind of package is usually sent by intermittent traffic;
8. The driver generally through the register to control PHY, such as auto-negotiation Speed/duplex, query the physical link status link up/down;
10. After the MAC is enabled, if there is no driver to set a bit of the control register (CTRL. SLU), Mac and PHY are not able to communicate, that is, Mac does not know that the PHY link is ready, so no data is received. After this setting, PHY completes self-negotiation, the NIC will have a link change interrupt, know that the physical connection has link up;
12. Even if link is up, the Mac needs a bit of the Enable receiver (RCTL. Rxen), the package can be received in, if the NIC is reset, this is 0, means that all the packets will be dropped directly, will not be stored in the network card FIFO. The old network card is used to turn off the receiver before the driver exits. Intel's latest gigabit network adapter sends the Receive Queue dynamic configuration is to rely on this bit, the reconfiguration process must turn off the traffic;
14. Regardless of whether the driver is loaded or not, after reset occurs, the MAC address of the NIC Eepom will write the MAC address filter Register of the network card, the driver can modify the register, and the modem network card usually supports many MAC addresses, that is, the MAC address can be set by the software. For example, Intel's Gigabit network card supports 16 unicast MAC addresses, but only 1 are in EEPROM, others are software claims and settings;
16. However, if the driver is not loaded, the NIC is already on the device tree, the operating system completes the initialization of step 1-2, and the PHY of the NIC should be working, but because no one is setting the control bit (CTRL. SLU) to make the Mac and PHY connect, so the Mac is not packet-wrapped. This control bit will be set to 0 when reset.
18. The PHY can be powered and powered down by the software, and the power-off state will not receive data except for receiving administrative commands. In addition, the PHY can also work in smart Power down mode, link down into the power-saving state;
20. Some multi-port network card, multiple network ports share a PHY, so the BIOS set Disbale a network port, also may not be the power to turn off the PHY, in turn, you have to carefully turn off the PHY power;
22. To learn more about PHY, you will eventually be familiar with IEEE Ethernet-related protocols.

This article refers to: http://blog.csdn.net/woodstar123/article/details/3324368

Network Port Literacy III: The relationship between Mac and PHY for Ethernet chips