Normal synchronous FIFO mode and Show-ahead synchronous FIFO mode

FIFO is a first-in, FIFO, can be used to handle the cross-clock domain data transmission problems, the use of a lot of places, be sure to engage in.

In the learning call FIFO IP core found in the normal synchronous FIFO mode and Show-ahead synchronous FIFO mode of the two modes, study it.

The most convenient way to study IP cores is to emulate them with Modesim, so the relationship will be clear.

The following two pictures are I use Time_gen software to summarize the painting, not Modesim simulation diagram.

Assume that the first number in the FIFO is 01, the second number is 02, the third number is 03, and so on ...

CLK is read clock, RD is read enable, q is FIFO data output

Normal mode only outputs the first number 01 when the read-enable signal is valid, when the reading clock rises.

The output of the Show-ahead mode is a shot earlier than the normal mode output, meaning that if there is data in the FIFO, he will output the first data,

When the first read enable signal comes in, it outputs a second data 02 when the read clock rises.

Normal Mode Show-ahead mode

Since the difference between the two is that the data output is not a beat, so in the design of the FIFO will be based on different patterns of design

For example, this code realizes the data transmission problem in different clock domains of 100Mhz and 80Mhz.

Due to the different frequency of different clock domains, data loss is inevitable if not processed during data transmission.

FIFO can cache data, so we can first put the data in FIFO, and then transfer

When the data in the FIFO resudw>= a certain number, it is not allowed to write to the FIFO, and the data is not allowed to be read when the FIFO is empty.

Module FIFO (
Rst_n, clk_in,//100Mhz, FIFO write clockdata_in,//input datadata_in_vld,//input Data valid indication signal clk_out,//80Mhz, FIFO read clockData_out,//Output datadata_out_vld,//output Data valid indication signal B_rdy//When high, indicating that the data read from the FIFO can be received, and vice versa) ; input rst_n, clk_in,clk_out,b_rdy;input [ the:0] data_in; input data_in_vld; output[ the:0] data_out; output[ the:0] Data_out_vld;reg wr_ff0;wire wr_ff1;wire[ the:0] q;reg[7:0] Data_out;reg data_out_vld;reg rd_ff0;wire rdempty; Wire wrfull; wire[5:0] WRUSEDW;
Call the IP core to generate a bit width of 16 bits, a FIFO with a depth of 64, Show-ahead mode My_fifo u1_fifo (. Data (data_in),. RDCLK (CLK                  _out),. Rdreq (RD_FF0),. WRCLK (Clk_in),. Wrreq (WR_FF1),                . Q (q),. Rdempty (Rdempty),. Wrfull (Wrfull),. WRUSEDW (WRUSEDW) );//----------------------------------------------------------------------//Write full protectionAlways @ (*) Beginif(wrusedw>= A) begin WR_FF0<=0; EndElsewr_ff0<=1; End Assign Wr_ff1= (DATA_IN_VLD && wr_ff0)?1'b1:1'B0;//rd_ff0Always @ (*) Beginif(b_rdy==1&&rdempty==0) begin RD_FF0<=1; EndElserd_ff0<=0; end//-------------------------------------------------------------
If the Show-ahead mode is in, the Data_out and DATA_OUT_VLD are aligned at this time
If it is normal mode, you need to take rd_ff0 more than one shot, then rd_ff1 value to DATA_OUT_VLD to align
always @ (Posedge clk_out or Negedge rst_n) beginif(rst_n==1'B0) Begindata_out<=0; EndElsebegin Data_out<=P; Endendalways @ (Posedge clk_out or Negedge rst_n) beginif(rst_n==1'B0) Begindata_out_vld<=0; EndElsebegin DATA_OUT_VLD<=rd_ff0; EndEnd

Endmodule

Article Source: http://www.cnblogs.com/aslmer/p/5872412.html

Normal synchronous FIFO mode and Show-ahead synchronous FIFO mode