Notes for start-up using OpenGL-Some Thoughts on sequential operations and parallel operations (refer to the tutorial of heijin: Modeling of those events using OpenGL)

It is a modeling language rather than a programming language. Compared with many programming languages, its biggest feature is parallelism. That is, in fact, it not only describes serial operations, but also describes parallel operations. If you understand the parallel design principles of the OpenGL, the designed system is not only well-defined, but also easy to understand and maintain.

For example, for the streaming lamp of programming entry, assuming the following functions are met: Three LED lights, each of which outputs a high level in three clock cycles, such as waveforms: led0, led1, led2 outputs high levels in turn.

If you use C programming, it may be like this:

While (1 ){

Led = 001; delay (1 );

Led = 010; delay (1 );

Led = 100; delay (1 );

}

We can see that the process of thinking is:

1: light the first light, delay;

2: Turn on the second light, delay;

3: Turn on the third light, delay;

4: Step 1

It can be seen that it is a typical sequential operation. 1 can be executed only after 1, and so on.

If we use parallel design:

Process 1: The first clock cycle led0 is on, and the last two clock cycles led0 is off

Process 2: The second clock cycle led1 is on, the first clock cycle and the third clock cycle led1 is off

Process 3: The third clock cycle led2 is on, and the first clock cycle and the second clock cycle led2 are off

Processes 1, 2, and 3 run in parallel without affecting each other.

In the OpenGL language, we can use parallel design or serial design.

Serial Design

　　

View code

 1 module flash(
 2     clk,rst_n,out
 3 );
 4     input clk,rst_n;
 5     output [2:0]    out;
 6     
 7     //the block of count
 8     reg [1:0] cnt;
 9     always @(posedge clk,negedge rst_n)
10         if(!rst_n)
11             cnt<=2'b0;
12         else if(cnt==2'b10)
13             cnt<=2'b0;
14         else
15             cnt<=cnt+1'b1;
16             
17     //the block of output
18     reg [2:0]    rOut;
19     always @(posedge clk,negedge rst_n)
20         if(!rst_n)
21             rOut<=3'b000;
22         else if(cnt<2'b1)
23             rOut<=3'b001;
24         else if(cnt>=2'b1 && cnt<2'b10)
25             rOut<=3'b010;
26         else
27             rOut<=3'b100;
28             
29     assign out=rOut;
30 endmodule

The following code demonstrates the serial design concept. The first light is lit in the first delay, the second light is lit in the second delay, and the third light is lit in the third delay.

View code

 1             else if(cnt<2'b1)
 2 
 3                      rOut<=3'b001;
 4 
 5               else if(cnt>=2'b1 && cnt<2'b10)
 6 
 7                      rOut<=3'b010;
 8 
 9               else
10 
11                      rOut<=3'b100;

Generated RTL View:

Although the generated RTL view shows that the three comparator are similar to parallel, it is still a serial design concept. The three lighting processes are sequential, and they are not mutually independent from each other. From lessthan0, we can see that the impact of the first delay judgment result is the input signal of the second delay judgment result: the second delay starts only after the first delay is completed. This is a typical idea of sequential operations.

Parallel design:

　　

View code

 1 module flash(
 2     clk,rst_n,out
 3 );
 4     input clk,rst_n;
 5     output [2:0] out;
 6     
 7     //the block of count
 8     reg [1:0]    cnt;
 9     always @(posedge clk,negedge rst_n)
10         if(!rst_n)
11             cnt<=2'd0;
12         else if(cnt==2'd2)
13             cnt<=2'd0;
14         else
15             cnt<=cnt+1'd1;
16     //the block of output led0;
17     reg rOut0;
18     always @(posedge clk,negedge rst_n)
19         if(!rst_n)
20             rOut0<=1'b0;
21         else if(cnt<2'b1)
22             rOut0<=1'b1;
23         else
24             rOut0<=1'b0;
25     //the block of output led1;
26     reg rOut1;
27     always @(posedge clk,negedge rst_n)
28         if(!rst_n)
29             rOut1<=1'b0;
30         else if(cnt>=2'b1 && cnt<2'b10)
31             rOut1<=1'b1;
32         else
33             rOut1<=1'b0;
34     //the block of output led2;
35     reg rOut2;
36     always @(posedge clk,negedge rst_n)
37         if(!rst_n)
38             rOut2<=1'b0;
39         else if(cnt==2'b10)
40             rOut2<=1'b1;
41         else
42             rOut2<=1'b0;
43     assign out={rOut2,rOut1,rOut0};    
44 endmodule

The output three always codes of led0, led1, and led2 in the above Code reflect the parallel design idea. In the Tilde language, the always block operates in parallel and does not affect each other.

Generated RTL View:

The RTL view above shows that the delay judgment statements of each always block do not affect each other and are directly connected to the output, reflecting the idea of parallel design. Compared with the serial design, the combination logic of the output end is simple, the RTL view is clear, easy to understand, and the RTL code is easy to maintain.

Through comparison, we can find that parallel design can better describe the system without consuming a lot of resources and satisfying the functions.

Note that it is meaningless to emphasize the simplicity of the Code in the Tilde language. Designers need to pay attention to how to model the system more vividly.