[Notes]. Several writing methods for the same duty cycle divider. [OpenGL]

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• 1, even division
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1 even Division (1) Power Division of 2

Case I dual-Division

I: div_2.v

 
Module div_2 (input I _clk, input I _rst_n, output o_clk); Reg [0: 0] CNT; always @ (posedge I _clk, negedge I _rst_n) if (! I _rst_n) CNT <= 0; else CNT <= CNT + 1 'b1; assign o_clk = CNT [0]; endmodule
 

II: RTL view (qii comprehensive results)

Figure 1 RTL view of Binary Division

III: simulation waveform (qii simulation results)

Figure 2 second-division simulation waveform

Case II quad-Division

I: div_4.v

Module div_4 (input I _clk, input I _rst_n, output o_clk); Reg [1:0] CNT; always @ (posedge I _clk, negedge I _rst_n) if (! I _rst_n) CNT <= 0; else CNT <= CNT + 1 'b1; assign o_clk = CNT [1]; endmodule
 

 II: RTL view (qii comprehensive results)

Figure 3 4-core RTL View

III: simulation waveform (qii simulation results)

Figure 4 four-frequency simulation waveform

(2) Power Division not 2

Case I six-Division

I: div_6.v

Module div_6 (input I _clk, input I _rst_n, output Reg o_clk); // log2 (6) = 2.5850 <= 3reg [] CNT; // 6 bit counter: 0 ~ 5 // 5 = 6-1 always @ (posedge I _clk, negedge I _rst_n) begin if (! I _rst_n) CNT <= 0; else begin if (CNT = 5) CNT <= 0; else CNT <= CNT + 1' B1; endend // 0 ~ 2-> 1 // 2 ~ 5-> 0 // 2 = 6> 1-1 // 5 = 6-1 always @ (posedge I _clk, negedge I _rst_n) begin if (! I _rst_n) o_clk <= 0; else begin if (CNT <= 2) o_clk <= 1; else o_clk <= 0; endend endmodule
 

II: RTL view (qii comprehensive results)

Figure 5 RTL View

GT;III: simulation waveform (qii simulation results)

Figure 6 6 6-frequency simulation waveform

Case II very frequent

I: div_10.v

Module div_10 (input I _clk, input I _rst_n, output Reg o_clk); // log2 (10) = 3.3219 <= 4reg [] CNT; // 10 bit counter: 0 ~ 9 // 9 = 10-1 always @ (posedge I _clk, negedge I _rst_n) begin if (! I _rst_n) CNT <= 0; else begin if (CNT = 9) CNT <= 0; else CNT <= CNT + 1' B1; endend // 0 ~ 4-> 1 // 4 ~ 9-> 0 // 4 = 10> 1-1 // 9 = 10-1 always @ (posedge I _clk, negedge I _rst_n) begin if (! I _rst_n) o_clk <= 0; else begin if (CNT <= 4) o_clk <= 1; else o_clk <= 0; endend endmodule
 

II: RTL view (qii comprehensive results)

Figure 7 RTL view with high frequency

III: simulation waveform (qii simulation results)

Figure 8 frequency simulation waveform

2 odd Division

Case I tri-Frequency

I. div_3.v

Module div_3 (input I _clk, input I _rst_n, output o_clk); // log2 (3) = 1.5850 <= 2 Reg [1:0] cnt_p; // rising edge count sub-// three rising edge counters: 0 ~ 2 // 2 = 3-1 always @ (posedge I _clk, negedge I _rst_n) begin if (! I _rst_n) cnt_p <= 0; else begin if (cnt_p = 2) cnt_p <= 0; else cnt_p <= cnt_p + 1 'b1; endend // log2 (3) = 1.5850 <= 2 Reg [1:0] cnt_n; // The descending edge of the counter sub-// The third descending edge of the counter: 0 ~ 2 // 2 = 3-1 always @ (negedge I _clk, negedge I _rst_n) begin if (! I _rst_n) cnt_n <= 0; else begin if (cnt_n = 2) cnt_n <= 0; else cnt_n <= cnt_n + 1 'b1; endend Reg o_clk_p; // output register of the rising edge clock // output the rising edge clock // 0 ~ 1 rows-> 1 // (1 + 1 )~ 2 rows-> 0 // 1 = 3> 1 // 2 = 3-1 always @ (posedge I _clk, negedge I _rst_n) begin if (! I _rst_n) o_clk_p <= 0; else begin if (cnt_p <= 1) // 1 = 3> 1 o_clk_p <= 1; else o_clk_p <= 0; endend Reg o_clk_n; // drop the output register along the clock // drop the output along the clock // 0 ~ 1 rows-> 1 // (1 + 1 )~ 2 rows-> 0 // 1 = 3> 1 // 2 = 3-1 always @ (negedge I _clk, negedge I _rst_n) begin if (! I _rst_n) o_clk_n <= 0; else begin if (cnt_n <= 1) // 1 = 3> 1 o_clk_n <= 1; else o_clk_n <= 0; endendassign o_clk = o_clk_n & o_clk_p; // bitwise AND (Role: mask) endmodule

II: RTL view (qii comprehensive results)

Figure 9 tri-frequency RTL View

III: simulation waveform (qii simulation results)

Figure 10 tri-frequency simulation waveform

Case II

I. div_5.v

Module div_5 (input I _clk, input I _rst_n, output o_clk); // log2 (5) = 2.3219 <= 3 Reg [] cnt_p; // rising edge count sub-// 5-digit rising edge counter: 0 ~ 4 // 4 = 5-1 always @ (posedge I _clk, negedge I _rst_n) begin if (! I _rst_n) cnt_p <= 0; else begin if (cnt_p = 4) cnt_p <= 0; else cnt_p <= cnt_p + 1 'b1; endend // log2 (5) = 2.3219 <= 3 Reg [] cnt_n; // descent along the Count subscriber // 5-digit descent along the counter: 0 ~ 4 // 4 = 5-1 always @ (negedge I _clk, negedge I _rst_n) begin if (! I _rst_n) cnt_n <= 0; else begin if (cnt_n = 4) cnt_n <= 0; else cnt_n <= cnt_n + 1 'b1; endend Reg o_clk_p; // output register of the rising edge clock // output the rising edge clock // 0 ~ 2 bytes-> 1 // (2 + 1 )~ 4 rows-> 0 // 2 = 5> 1 // 4 = 5-1 always @ (posedge I _clk, negedge I _rst_n) begin if (! I _rst_n) o_clk_p <= 0; else begin if (cnt_p <= 2) // 2 = 5> 1 o_clk_p <= 1; else o_clk_p <= 0; endend Reg o_clk_n; // drop the output register along the clock // drop the output along the clock // 0 ~ 2 bytes-> 1 // (2 + 1 )~ 4 rows-> 0 // 2 = 5> 1 // 4 = 5-1 always @ (negedge I _clk, negedge I _rst_n) begin if (! I _rst_n) o_clk_n <= 0; else begin if (cnt_n <= 2) // 2 = 5> 1 o_clk_n <= 1; else o_clk_n <= 0; endendassign o_clk = o_clk_n & o_clk_p; // bitwise AND (Role: mask) endmodule

II: RTL view (qii comprehensive results)

Figure 11 RTL View

III: simulation waveform (qii simulation results)

Figure 12 5-frequency simulation waveform

References

1. How can I deploy the calculator? (SOC) (sparse core)

Http://www.cnblogs.com/oomusou/archive/2008/07/31/verilog_clock_divider.html

2. The hour does not know the month, and the N-odd number divider)

Http://blog.ednchina.com/2006tx_yafeng/146438/message.aspx

3. I don't know the month in small hours, n times the even number of divider. (OpenGL)

Http://blog.ednchina.com/2006tx_yafeng/146525/message.aspx