/**************************************************************************************** * OK 335xS u-boot Gpio Control hacking * Declaration: * This article is mainly to track how to set the GPIO port level in U-boot. * 2015-9-26 Sunny Shenzhen Nanshan Ping Shan village Zengjianfeng ******************************************** *******************************************/Cat Board/forlinx/ok335x/EVM.CintBoard_init (void) { intc = -; /*Configure the i2c0 pin MUX*/Enable_i2c0_pin_mux (); I2c_init (Config_sys_i2c_speed, Config_sys_i2c_slave); board_id=Gp_board; profile=1;/*Profile 0 is internally considered as 1*/daughter_board_connected=1; Configure_evm_pin_mux (board_id, header.version, profile, Daughter_b oard_connected); --+ |/** | * 1. References: | * am335x ARM Cortex-a8 microprocessors (mpus) Technical Reference Manual (Rev. H) | * | * 2. ARM cortex-a8 Memory Map | * Table 2-2. L4_wkup Peripheral Memory Map (continued) | * +-------------+---------------------+-------------------+------+----------------+ | * | Region Name | Start Address (hex) | End Address (hex) | Size | Description | | * +-------------+---------------------+-------------------+------+----------------+ | * | GPIO0 | 0x44e0_7000 | 0X44E0_7FFF | 4KB | GPIO Registers | | * +-------------+---------------------+-------------------+------+----------------+ | * | * 3. GPIO registers (4068 pages) | * Table 25-5. GPIO Registers | * +--------+-------------------+---------------+-------------------+ | * | Offset | Acronym | Register Name | Section | | * +--------+-------------------+---------------+-------------------+ | * | 134h | Gpio_oe | | Section 25.4.1.16 |<-+ | * +--------+-------------------+---------------+-------------------+ | | * | 190h | Gpio_cleardataout | | Section 25.4.1.25 | |<-+ | * +--------+-------------------+---------------+-------------------+ | | | * | 194h | Gpio_setdataout | | Section 25.4.1.26 | | |<-+ | * +--------+-------------------+---------------+-------------------+ | | | |*/| | | |/*set gpio0_7 Gpio0_12 gpio0_22 gpio0_23 output mode*/| | | |__raw_writel (~((1<<7) | (1<< A) | (1<< A) | (1<< at)),0x44e07134);-------+ | | |/*Set Gpio0_7*/| | |__raw_writel ((1<<7) | (1<< +) | (1<< at),0x44e07190); ----------+ | |/*set gpio0_22 high to height*/| |__raw_writel ((1<< A) | (1<< A),0x44e07194); -------------+ | | |#ifndef Config_spl_build|Board_evm_init (); |#endif|Gpmc_init (); | |return 0; | } +-------------------------------------------------------------------------+VvoidConfigure_evm_pin_mux (unsignedCharDGHTR_BRD_ID,Charversion[4], unsigned ShortProfile , unsignedintDaughter_board_flag) { if(dghtr_brd_id >Base_board)return; Set_evm_pin_mux (am335x_evm_pin_mux[0], Profile,daughter_board_flag); } |V Static structEvm_pin_mux *am335x_evm_pin_mux[] ={General_purpose_evm_pin_mux,----------------------+ }; | |/* | * Update the structure with the modules present in the general purpose | * Board and the profiles in which the modules is present. | * If the module is physically present if it isn't available | * In any of the profiles, then does not update it. | * For EG, NAND was avialable only in the profiles 0 and 1, whereas | * UART0 is available in all the profiles. | */|Static structEvm_pin_mux general_purpose_evm_pin_mux[] = {<----------+{i2c1_pin_mux, Profile_all& ~profile_2 & ~profile_4, Dev_on_baseboard}, #ifdef Config_nand {Nand_pin_mux, Profile_all& ~profile_2 & ~profile_3, DEV_ON_DGHTR_BRD},#endif #ifndef Config_no_ ETH {mii1_pin_mux, Profile_all, Dev_on_b Aseboard},#endif #ifdef CONFIG_MMC {Mmc0_pin_mux, Profile_all, Dev_on_b Aseboard},#endif {backlight_pin_mux, Profile_all, Dev_on_baseboard},-----+{maxttl_model_pin_mux, Profile_all, Dev_on_baseboard},|{lcd_pin_mux, Profile_all, Dev_on_baseboard},|{uart0_pin_mux, Profile_all, Dev_on_baseboard},| {0}, | }; | |Static structModule_pin_mux backlight_pin_mux[] = {<----+{OFFSET (ecap0_in_pwm0_out), MODE (7) | Pullup_en | Rxactive},/*gpio0_7*/{OFFSET (UART1_CTSN), MODE (7) | Pulluddis | Rxactive},/*gpio0_*/ {-1}, };
Ok335xs u-boot GPIO Control hacking