Ok6410 clock notes

The following figure shows the system clock schematic of 6410:

Of

Formula for determining the clock frequency of 6410: fout
= Mdiv * FIN/(pdiv * 2 ^ sdiv) The values (mdiv, pdiv, sdiv) are in apll_con and mpll_con. Fin is the input clock of our system, and ok6410 is 12 MHz.

To get the final output clock, you must set the DIV divider.
Armclk = doutapll/(arm_radio + 1)

Clk_div0 mainly controls the system clocks and special
Clocks of multimedia ip s. The output frequencies
Apll and mpll are divided by arm_ratio and mpll_ratio. hclkx2 clock is the base clock of other
Operating system clocks and divided by hclkx2_ratio. There is operating frequency limitation. The maximum
Operating frequency of hclkx2, hclk, and pclk are 266 MHz, 133 MHz, and 66 MHz, respectively. nand,
Secur, JPEG operating clock cannot exceed 66 MHz. MFC and Cam operating clock cannot exceed 133 MHz.
This operating clock condition must be met through clk_div0 configuration.

This is a passage in the manual, that is, the frequency of hclk * 2 cannot exceed 266 MHz. JPEG and Cam frequencies are limited.

Apll to arm
CPU usage
Mpll is provided to the master device, hclk (memory, DDR), and pclk (peripheral chip module)
Epll to other modules

Asynchronous mode: Others registers are set to asynchronous mode.
Read the others memory value and clear the BIC 0xc0
Set it to asynchronous when the arm clock is different from the hclk clock.

Loop judgment, waiting for the setting to complete

Frequency Division settings: to make our clock work normally, we also need to set the corresponding frequency division parameters, as shown below:

The frequency division parameter is mainly set in clk_div0.

 
Set clk_dvio
Set arm_ratio 0 primary core to 1
Set hclckx2_ratio 1 to divide the input clock by two
Set hclk_ratio 1 and then divide the input clock into two groups for memory usage.
Set pclk_ratio 3 other ratio settings

Procedure:

 

/*************************************** * ********************************** // Name: system clock setting * // * parameters: arm_clk = 532 hclk = 133 hclkx2 = 266 pclk = 66.5 *//************************* **************************************** * ******/# define rapll_lock (* (volatile unsigned long *) 0x7e00f000) # define rmpll_lock (* (volatile unsigned long *) 0x7e00f004) # define repll_lock (* (volatile unsigned long *) 0x7e00f008) # define Rapll_con (* (volatile unsigned long *) # define rmpll_con (* (volatile unsigned long *) 0x7e00f010) # define rclk_src (* (volatile unsigned long *) 0x7e00f01c) # define rclk_div0 (* (volatile unsigned long *) 0x7e00f020) # define rclk_div1 (* (volatile unsigned long *) 0x7e00f024 )) # define rclk_div2 (* (volatile unsigned long *) 0x7e00f028) # define rothers (* (volatile unsigned long *) 0x7e00f900) # Define arm_ratio 0/* armclk = doutapll/(arm_ratio + 1) */# define hclkx2_ratio 1/* hclkx2 = hclkx2in/(hclkx2_ratio + 1) */# define hclk_ratio 1/* hclk = hclkx2/(hclk_ratio + 1) */# define pclk_ratio 3/* pclk = hclkx2/(pclk_ratio + 1) */# define mpll_ratio 0/* doutmpll = moutmpll/(mpll_ratio + 1) */# define sdiv 1 # define pdiv 3 # define mdiv 266 # define en 1 // enable pllvoid clock_init () {rapll _ Lock = 0x0000ffff; rmpll_lock = 0x0000ffff; repll_lock = 0x0000ffff; // rothers ~ (3 <6); // set the clock to asynchronous mode while (rothers & 0xf00 )! = 0); // wait for the asynchronous mode to enter rclk_div0 = arm_ratio | (mpll_ratio <4) | (hclk_ratio <8) | (hclkx2_ratio <9) | (pclk_ratio <12); // set the frequency division parameter rapll_con = sdiv of clk_div0 | (pdiv <8) | (mdiv <16) | (EN <31 ); // set fout = 532mrmpll_con = sdiv | (pdiv <8) | (mdiv <16) | (EN <31 ); // set fout = 532mrclk_src = 0x03; // select the clock source}

In the Assembly startup code, you can set the clock by adding a sentence before jumping to the main function.
BL clock_init

Main function. I wrote the code for the streaming lamp according to the video instruction of teacher Wei Dongshan. We can see that if the delay is not enough, the streaming lamp runs very fast.