One of de2-115 Ethernet communication 88E1111 network card receiving PC data

To use the de2-115 on hand to write a driver about Ethernet communication, after so many days of experimental debugging finally have some knowledge.

1, I observed the network card to send data and receive data, I found that I send data from a network card on the FPGA, and then another network card to receive data, the received data will be in front of the 55h 8bit of data. I send data from the PC and receive the data with the NIC on the FPGA, then there will be 55H,55H,55H,55H,55H,55H,55H,5DH 64bit data in front of the received data. So if 55h this 8bit data is automatically added when PHY is sent then the last received from the PC should be 55 instead of 5d. Then only the network card is automatically added at the time of receiving 55h this 8bit bit. The rest of the 56bit should be added to the data itself.

2, I use Signaltap II set the sampling frequency is 50Mh, and the data bandwidth is 100Mhz. When I use the Creep Ethernet tester set to send frequency of 1000000/times, found that Siganltap II Rx_data data for a long time to change, the rest of the time is zero, but with the led by the reception of data to observe the frequency of the transmission, then signal Tap II Scenarios where the data cannot be observed for a long time should be related to the setting of the clock.

3, for a period of time I send data from the PC, and then the data received on the FPGA, an individual bit of data error occurred. When I set the configuration of the two PHY on the board to be correct. will be able to receive the data correctly.

4, SIGNALTAP received PC data high four-bit and the fourth position upside down, for example, if the data sent is 56h 75h 83h then received data is 65h 57h 38h. Indicates that the data is sent in the process high first send low four bit after sending high four bits.

5, 88E1111 with 100M, full duplex can receive data from the PC register settings.

A, PHY's physical address is 10000, board connection JP1 23.

b, read register and write register. The read register is primarily intended to observe if the PHY is configured correctly. It is important to read the registers correctly during the debugging process.

The code is as follows

1 if(flag)begin 2          Case(Mdc_num)3           0:beginrst_n<=0; mdio_reg<=mdio_reg+1;if(mdio_reg& +'hffffffff==32'HFFFFFFFF)beginrst_n<=1; mdc_num<=1;End 
Elsemdc_num<=0;End4           1:beginmdio_reg<= the'hffff_ffff__585a__0000_ffff_ffff;mdc_num<=2;end//select Page0 copper5           2:beginmdc_count<=mdc_count+1;6           if(mdc_count< the)beginmdio<=mdio_reg[ the]; wr_rd<=1;mdio_reg<=mdio_reg<<1; mdc_num<=2;End 7                       Else beginmdc_num<=5; mdc_count<=0;End End   One           5:beginmdio_reg<= the'hffff_ffff__5812_0101_ffff_ffff;mdc_num<=6;end//4 100full duplex,802.3 A           6:beginmdc_count<=mdc_count+1; 　 if(mdc_count< the)beginmdio<=mdio_reg[ the]; wr_rd<=1;mdio_reg<=mdio_reg<<1; mdc_num<=6;End  -                       Else beginmdc_num<=9; mdc_count<=0;End End                   9:beginmdio_reg<= the'hffff_ffff__5826__0400_ffff_ffff;mdc_num<=10;end//9 Automatic master-slave, multi port device +           Ten:beginmdc_count<=mdc_count+1;  if(mdc_count< the)beginmdio<=mdio_reg[ the]; wr_rd<=1;mdio_reg<=mdio_reg<<1; mdc_num<=Ten;End                          Else beginmdc_num<= -; mdc_count<=0;End End   A            -:beginmdio_reg<= the'hffff_ffff__5842__0068_ffff_ffff;mdc_num<=14;end//16 Power up -            -:beginmdc_count<=mdc_count+1; if(mdc_count< the)beginmdio<=mdio_reg[ the]; wr_rd<=1;mdio_reg<=mdio_reg<<1; mdc_num<= -;End  　　　　　　　　　　　　　　  Else beginmdc_num<= -; mdc_count<=0;End End      2   -:beginmdio_reg<= the'hffff_ffff__5852_9051_ffff_ffff;mdc_num<=18;end//9051 to            -:beginmdc_count<=mdc_count+1;if(mdc_count< the)beginmdio<=mdio_reg[ the]; wr_rd<=1;mdio_reg<=mdio_reg<<1; mdc_num<= -;End  　　　　　　　　　　　　　　　　  Else beginmdc_num<= +; mdc_count<=0;End End   the            +:beginmdio_reg<= the'Hffff_ffff__5802_a100_ffff_ffff;mdc_num<=20;end *            -:beginmdc_count<=mdc_count+1;  if(mdc_count< the)beginmdio<=mdio_reg[ the]; wr_rd<=1;mdio_reg<=mdio_reg<<1; mdc_num<= -;End  　　　　　　　　　　　　　　　　  Else beginmdc_num<= +; mdc_count<=0;End  End -            +:beginmdc_count<=mdc_count+1;if(mdc_count< +)beginmdio<=1'B1; Wr_rd<=1;mdc_num<=21;end $              Else beginflag<=0; wr_rd<=0;End  End -           Endcase 

End  -        Else the             begin -     Wuyi                     Case(Timenum) the                          0:beginmdio_reg<= the'b11111111111111111111111111111111_01101000010001z1_zzzzzzzzzzzzzzzz_11111111111111111111111111111111; Timenum<=1;wr_rd<=1;mdc_count<=0;end -                          1:beginmdc_count<=mdc_count+1;if(mdc_count< -)beginmdio<=mdio_reg[ the]; mdio_reg<=mdio_reg<<1; timenum<=1;End Else beginwr_rd<=0; timenum<=2;End End  Wu                           2:begindata1[ the]<=mdio_in;timenum<=3;End -                           3:begindata1[ -]<=mdio_in;timenum<=4;End About                           4:begindata1[ -]<=mdio_in;timenum<=5;End $                           5:begindata1[ A]<=mdio_in;timenum<=6;End -                           6:begindata1[ One]<=mdio_in;timenum<=7;End -                           7:begindata1[Ten]<=mdio_in;timenum<=8;End -                           8:begindata1[9]<=mdio_in;timenum<=9;End A                           9:begindata1[8]<=mdio_in;timenum<=Ten;End +                           Ten:begindata1[7]<=mdio_in;timenum<= One;End the                            One:begindata1[6]<=mdio_in;timenum<= A;End -                            A:begindata1[5]<=mdio_in;timenum<= -;End $                            -:begindata1[4]<=mdio_in;timenum<= -;End the                            -:begindata1[3]<=mdio_in;timenum<= the;End the                            the:begindata1[2]<=mdio_in;timenum<= -;End the                            -:begindata1[1]<=mdio_in;timenum<= -;End the                          　  -:begindata1[0]<=mdio_in;mdc_count<=1; timenum<= -;End -                            -:beginmdc_count<=mdc_count+1; wr_rd<=1; mdio<=1;if(mdc_count==7'h3f) mdc_count<=0;timenum<=0; End in                     Endcase  the              the             End 

One of de2-115 Ethernet communication 88E1111 network card receiving PC data