One of my RTOS -- s5pv210 abnormal vector table base address and Soft Interrupt Test

1. Base Address of the abnormal vector table

S5pv210 specifies the base address of the exception vector 0xd003_4700 by default. When an exception is triggered, such as an interrupt, the base address of the exception vector 0xd003_4700 is specified by default in s5pv210, will automatically jump to the base address to find the exception handling function

This can be achieved through code, and through code,

#define_Exception_Vector0xD0037400#define pExceptionRESET( *((volatile unsigned long *)(_Exception_Vector + 0x0)) )#define pExceptionUNDEF( *((volatile unsigned long *)(_Exception_Vector + 0x4)) )#define pExceptionSWI( *((volatile unsigned long *)(_Exception_Vector + 0x8)) )#define pExceptionPABORT( *((volatile unsigned long *)(_Exception_Vector + 0xc)) )#define pExceptionDABORT( *((volatile unsigned long *)(_Exception_Vector + 0x10)) )#define pExceptionRESERVED( *((volatile unsigned long *)(_Exception_Vector + 0x14)) )#define pExceptionIRQ( *((volatile unsigned long *)(_Exception_Vector + 0x18)) )#define pExceptionFIQ( *((volatile unsigned long *)(_Exception_Vector + 0x1c)) )void system_vector_init( void){pExceptionRESET  = (unsigned long)exceptionreset;pExceptionUNDEF  =(unsigned long)exceptionundef;pExceptionSWI    =(unsigned long)SWI_handle;pExceptionSWI1= (unsigned long)exceptionswi;pExceptionPABORT  =(unsigned long)exceptionpabort;pExceptionDABORT  =(unsigned long)exceptiondabort;pExceptionIRQ  =(unsigned long)IRQ_handle;pExceptionFIQ  =(unsigned long)exceptionfiq;}

Although the IRQ interrupt can be successfully redirected, the SWI Soft Interrupt fails.

No reason was found for searching the Samsung manual.

2. The base address of the exception vector can be set.

S5pv210 also sets the vector base address as the high address through the coprocessor, or maps the base address to any place in the memory through MMU, but it has more flexible functions and can set the base address of the exception vector to any place, this facilitates bare metal transplantation and RTOS migration.

S5pv210 can be used to set the base address of an exception vector in three modes (security mode monitoring mode and non-security mode.

Through the test, the SWI Soft Interrupt Test is successful by setting the base address of the exception vector.

Set the base address of the exception vector in current mode by modifying C12:

.global _set_interrupt_vector_set_interrupt_vector:mcrp15, 0, r0, c12, c0, 0mrcp15, 0, r0, c12, c0, 0mov pc, lr

In the C code, you can also read the base address of the vector.

static inline unsigned int get_vectors_address(void){    unsigned int temp;    /* read SCTLR */__asm__ __volatile__(   "mrc p15, 0, %0, c1, c0, 0\n":"=r"(temp):);    if (temp & (1<<13))        return (unsigned int ) 0xffff0000;    /* read VBAR */    __asm__ __volatile__("mrc p15, 0, %0, c12, c0, 0\n"            : "=r" (temp) : );    return (unsigned int ) temp;}

3. Soft Interrupt

"Swi xxx" or "svc xxx" can trigger Soft Interrupt. xxx must be an immediate number, not a register.

After a Soft Interrupt is triggered, the processor automatically saves the next SWI command to the LR in SVC mode and saves the current cpsr to the spsr in SVC mode. SWI must have a command and can run normally.

Therefore, the SWI trigger function can be implemented in this way.

switest:stmfdsp!, {fp, lr}swi 0x8ldmfd sp!, {fp, pc}

The next SWI command can place the operations after the SWI interrupt is completed to the end of the switest function.

The SWI processing function can be completed as follows:

swi_handle:stmfdsp!, {r0-r12, lr}mov r1,r0mrs r0,spsrstmfdsp!,{r0}tst r0, #0x20ldrne r0, [lr, #-2]bicne r0, r0,#0xff00ldreq r0, [lr, #-4]biceq r0, r0,#0xff000000bl c_swi_handlerldmfdsp!,{r0}msr spsr_cf, r0ldmfd sp!, {r0-r12, pc}^

First, save the register and then save the spsr. Because I don't know whether an exception occurs again during SWI processing, check whether the C program is compiled by thump. Therefore, we need to check the thump flag of the spsr. After the processing is complete, the processor returns the mode from SVC mode to the mode before SWI is executed.

4. program running

Timer0IntCounter = 0 Timer0IntCounter = 1 Timer0IntCounter = 2 swi test:1c_swi_handler:8,arg:3Timer0IntCounter = 3 Timer0IntCounter = 4 Timer0IntCounter = 5 swi test:2c_swi_handler:8,arg:6Timer0IntCounter = 6 Timer0IntCounter = 7 Timer0IntCounter = 8 swi test:3c_swi_handler:8,arg:9Timer0IntCounter = 9 Timer0IntCounter = 10 Timer0IntCounter = 11 swi test:4

Demo link http://download.csdn.net/detail/liujia2100/8102515

One of my RTOS -- s5pv210 abnormal vector table base address and Soft Interrupt Test