Operating system chapter-Analysis of paging mechanism

Tag: Control occupies memory capacity part processing opens the specified field

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First, preface

In our program development, in general, do not need to manage memory, do not need to worry about memory enough to use, in fact, this is the paging mechanism to bring us the benefits. It is the key to implementing virtual storage, between a linear address and a physical address, where each executing process (Task) can use a contiguous address space that is much larger than the actual memory capacity when using this memory paging management method. And when the system memory is actually broken into a lot of messy chunks, it can create a large and contiguous image of the memory space so that the program does not have to worry about and manage these scattered memory blocks. The paging mechanism enhances the performance of the staging mechanism. Page address transformations are built on the basis of segment transformations. Because the segment management mechanism is the most basic for Intel processors, it cannot be shut down at any time. So even if the page management feature is enabled, the staging mechanism still works, and the segment part still works.

　　Second, page table structure

So how does the paging mechanism work? The paging mechanism can be turned on by setting the PG bit of the CR0 . The page size is 4K and is 4K aligned. When a linear address is converted to a physical address by a paging mechanism, some linear addresses may be invalid. If the page that corresponds to a linear address does not exist, then an exception is generated when the access occurs.

　　Level two page table structure

The basic principle of memory paging management is to divide the entire main memory region into 4096-byte pages of memory. When a program requests to use memory, it is allocated in memory pages. The above mentioned that the linear address has been transformed into a physical address through the paging mechanism, but there is no mention of how to convert it. In fact, through two tables, one is the page catalog table Pde, also known as a first-level directory, and the other is a two-level page table Pte. The virtual address of a process needs to be transformed first through its local segment descriptor into the address in the entire linear address space of the CPU, and then mapped to the actual physical Address page using the page Catalog table PDE (first-level page table) and the page table PTE (Level two page table). In the page table, the size of each item is 32b, where 20b is used to hold the physical address of the page, and 12b is used to store the property information. The page table contains 1M table entries, each of which is 4 B. The first Level table is a page directory, stored in a 1-page 4k page, containing 1K of table entries. The second level is the page table, which is also a 1K table item. As shown in the following:

　　Third, structure

　　

PDE structure

PTE Structure

From this, it can be seen that PDE and PTE structure is actually similar, where the attribute bit contains the following information:
P--bit0, a bit flag that indicates whether the page or page table pointed to by the current entry is in physical memory;
R/w--bit1, read-write bit flags that specify read and write permissions for a page or a set of pages. R/w=0 means read-only, r/w=1 readable and writable;
U/s--bit2, user/Superuser flag, specifies the privilege level of a page or a set of pages;
PWT--BIT3, which controls the Write-back or Write-through buffering strategy for a single page or page table;

PCD--BIT4, which controls the buffering of individual pages or page tables;

A--BIT5, indicates whether the page or page table is accessed;
D--BIT6, indicates whether the page or page table is written;

PS--BIT7, determines the size of the page;

G--BIT8, indicating the global page;

avl--reserved Fields;

Whether the protection mode is on depends on the No. 0 pg of the CR0. A page table or page catalog item size is 4B, and after the paging mechanism is turned on, the storage unit becomes a page (no, some stores have a paging mechanism turned on, and the other part does not have a paging mechanism (unless this part is accessible through the operating system)). Therefore, a page contains 1024 page table items, a page directory, corresponding to the 1k*4k=4m space, a program has a 4G linear address space, just need 1K page directory to store, it occupies the page table is 4M.
In addition, both the page table and the page catalog table entries are 32b, where the address corresponds to 20b. The processor saves the most frequently used page and page table entries in the TLB. And what is a TLB? It is simple to understand that the TLB is the cache of the page table, which stores the page table entry that is most likely to be accessed, and whose content is a copy of the partial page table item. The page table is queried in memory only if the TLB is unable to complete the address translation task, reducing the processor performance degradation caused by page table queries.
When the page directory or page table entry is modified, the items corresponding to the TLB are invalidated, and when CR3 reloads, all TLB are invalidated, unless the G-bit of the page or page table entry is set.

Is the structure of CR3, CR3 is also called PDBR, is the page directory register. Its high 20 bits will be high 20 bits of the top address of the page catalog table, the low 12 bits of the page catalog table will be zero, that is, the page catalog table will be 4KB aligned. Similarly, page table base addresses in the Pde and page base addresses in PTEs are also page tables and pages that represent 4KB alignment with a high 20-bit.

　　Iv. Summary

Recall that the above is not a lot of content, mainly this part is the basis of understanding the system, including the following points:

1. The role of paging, efficient use of memory, can run more than the physical memory space of the program;

2. The principle of paging mechanism, using the two-level page table to divide the memory into 4kb/page size, forcing memory alignment to improve efficiency;

3. Page table structure, PDE and Pte in memory of the main role of each bit, table items and the corresponding relationship between the page.

Previous several share, all mentioned a lot of principles, nonsense, the next chapter begins we will use code to gradually explain, I hope you continue to pay attention!!

Operating system chapter-Analysis of paging mechanism