Orange's implementation of an operating system 3. Protection Mode 8-page storage

Source: Internet
Author: User
Orange & rsquo; s implementation of an operating system 3. Protection Mode 8-webpage storage Author: aoysme | Source: blog garden | 21:12:59 | read 19 times

A. Overview of paging mechanism ()

The segmentation part is a segmentation mechanism. The logical address uses the segment to select a child, and the base address of the segment is determined from the segment descriptor corresponding to the gdt. Then, the offset is added to determine the linear address.

Paging is paging: physical address = f (linear address)


The paging mechanism uses two-level conversion tables. The first level is called the page Directory, which is stored in a physical page. The size is 4 kb and each table item is 4 bytes,

There are a total of 1024 table items (page directory entry ).

Each table item corresponds to a page table at the second level, and each page table also has 1024 items (page table entry). Each table item corresponds to a physical page.

 

When the conversion is run, the page table address is obtained in the page directory specified by the Register ("dir" in the figure) based on the high 10 bits of the linear address, and then

12 to 21 digits (table in the figure) Get the physical header address, and add the first address with a linear address of 12 digits (offset in the figure) to get the physical address.

 

If the paging mechanism is effective, the switch is at most PG bit in Cr0, Pg = 1, and the page takes effect. So when we have prepared the page Directory table and page table

After the page Directory table, you only need to reset the PG bit to start the paging mechanism.

 

B. PVDF and PTE


P existence bits: indicates whether the page or page table pointed to by the current entry is in physical memory. p = 0, indicating that the page is not in memory. If the processor attempts to access this page
Page-caused exception (# PF); P = 1 indicates that the page is in memory

 

R/W specifies the read and write permissions for a page or a group of pages. R/W = 0 indicates read-only, R/W = 1 indicates read and write.

This bit interacts with WP in U/S bit and Cr0

 

U/s specifies the privileged level of a page or a group of pages. This bitwise interacts with WP in R/W and Cr0.

U/S = 0 indicates the system level. If CPL =, 2 indicates the system level.

U/S = 1, indicating the system level. If CPL = 3

If the WP of Cr0 is 0, the system-level program still has write permission even if the R/W of the user-level page is 0.

WP = 1. Even if R/W = 0 for user-level pages, system-level programs cannot write read-only pages.

PWT is used to control the buffer policy for a single page or page table. PWT = 0 use the write-back buffer Policy
PWT = 1 use the write-through buffer Policy

When the cache-Disable bit of Cr0 is set, it is ignored.

When the buffer size for a single page or page table is 0, the page or page table can be buffered with 1.

When the cache-Disable bit of Cr0 is set, it is ignored.

A Indicates whether a page or page table is accessed. When a page or page table is loaded into the physical memory, it is cleared by the Memory Manager.

This bit is set when you access this page or page, and the processor does not automatically clear this bit. Only software can clear it

D indicates whether the page or page table is written. When a page or page table is loaded into the physical memory, it is cleared by the Memory Manager.

This bit is set when you access this page or page, and the processor does not automatically clear this bit. Only software can clear it

Both a-bit and D-bit are used by the memory management program to manage pages and page tables for switching from the physical memory.

 

PS bit determines the page size PS = 0 the page size is 4 kb, and PDE points to the page table

Pat: select the PAT (page Attribute Table) entry.

G indicates the global page. If this bit is set, the PGE bit in CR4 is also set. The page table and page directory entries on this page will no longer become invalid in TLB.

The processor saves frequently used page directories and page tables in a buffer called TLB (translation lookasied buffer ).

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