Overview of New vro Technologies

Currently, several new technologies that play a key role in improving the performance of routers mainly include the following: first, more and more functions are implemented in hardware mode, the improvement of CMOS integration technology enables many functions to be implemented on dedicated ic asic chips. The functions originally implemented by software can now be completed by faster hardware and lower costs, the system performance is greatly improved. Second, the distributed processing technology is adopted in routers, which greatly improves the routing processing capability and speed of routers. Third, the shared bus that is easy to cause congestion is gradually abandoned, the exchange routing technology is widely used in the beginning. In the exchange structure design, the design of the internal interconnection network of the giant computer or the introduction of the optical switching structure is adopted. In addition, the rapid search technology of Route tables, QoS Assurance, and the use of MPLS technology to optimize the future network, and the introduction of optical switching in routers are also receiving increasing attention. The new technologies of routers mainly refer to innovations in these aspects.
I. ASIC Technology
Because manufacturers need to reduce costs, ASIC technology has been widely used in routers. In a vro, to greatly increase the speed, the first thing you don't think of is ASIC. ASIC can be used for packet forwarding and querying routing. At present, there is a commercial ASIC chip dedicated to finding IPV4 routes. The Application of ASIC Technology significantly improves the packet forwarding speed and route search speed in the vro.
Express routers separate non-real-time tasks such as route computing and control from real-time tasks such as data forwarding. Non-real-time tasks such as route computing and control are completed by the CPU running software, and real-time tasks such as data forwarding are completed by dedicated ASIC hardware. Since the second half of 1997, some companies have successively launched new routers that use dedicated Integrated Circuits (ASIC) for route identification, computing, and forwarding. The forwarder is responsible for all data forwarding functions. This type of router uses hardware to forward data packets one by one according to the cycle of the clock to achieve line rate forwarding.
The development of ASIC Technology means that more features can be moved to the hardware, improving the performance and adding features. Compared with software execution, ASIC has three times the performance of the latter. However, all-hardware vrouters lack flexibility and take some risks because the standard specification is still evolving, so programmable ASIC is emerging. Programmable ASIC is the development trend of ASIC because it can adapt to network structure and protocol changes by rewriting microcodes. Currently, there are two types of Programmable ASIC: one is represented by the FIREFlexible Intelligent Routing Engine chip of 3Com, and the other is represented by the HISC dedicated chip of Vertex Networks, this chip is a dedicated CPU designed for communication protocol processing. By Rewriting the microcode, the chip has the ability to process different protocols.
Ii. Distributed Processing Technology
The original router adopted the traditional computer architecture, including the shared central bus, central CPU, memory, and multiple network physical interfaces mounted on the shared bus. The interface card sends packets to the CPU through the bus, and the CPU completes route calculation, query table, and forwarding decision processing, and then sends the packets to another physical interface through the bus. The main limitation of a Single-bus single CPU is that the processing speed is slow. A single CPU completes all the tasks, thus limiting the system throughput. In addition, the system has poor fault tolerance. If the CPU fails, the system may be completely paralyzed. All of this makes it difficult to greatly improve the forwarding performance of traditional routers.
Modern routers adopt distributed processing for packet forwarding, and can insert multiple line processing boards. Each circuit board completes the forwarding process independently, that is, each interface has an independent CPU, it is responsible for receiving and sending the interface data packets separately, managing the receiving and sending queues, querying the route table, and making forwarding decisions. The core switching board is used to realize non-blocking exchange between boards. That is, after a packet input on a board is routed, it can be exchanged to another board for output as directly connected through a wire, the throughput of the entire machine can be multiplied. The master CPU only provides non-real-time functions such as vro configuration control and management. The advantage of this architecture is that the local forwarding/filtering of data packets is determined by the dedicated CPU processed by each interface, and the packet processing is distributed to each interface card. The circuit board has a dedicated chip to complete layer-2, layer-3, or even layer-4 forwarding. The hardware enables forwarding to reach the speed of the connection link of the line speed high-speed port, so that the router will not become a bottleneck in the network.
However, the biggest drawback of a Single-bus router is that only one group can be switched from the entry to the exit at a time. If multiple data transmission channels exist between the entry and exit, this problem can be solved and the system throughput can be greatly improved. Based on this idea and the advantages of the ATM switch structure, a new generation router architecture based on the switch structure shown in 3 is proposed.
Iii. Exchange Routing Technology
Although the computer industry has introduced more and more high-speed shared bus in recent years, from ISA to EISA to the current PCI. However, this still cannot keep up with the pace of network development. First, the shared bus cannot avoid internal conflicts. Second, the load effect of the shared bus makes the design of the high-speed bus too difficult.
1. Single-Stage switching structure
The introduction of the switching structure gradually overcomes the shortcomings of the shared bus. Technically, many swap structures are currently used: Shared Memory and Crossbar. The structure of Crossbar is more favored and widely used due to its simplicity.
The shared memory structure shares the buffer of the input and output ports to reduce the total storage space requirements. Group switching is implemented through pointer calls, which increases the switching capacity. However, its speed is limited by the memory access speed.
The Crossbar structure can provide multiple data paths at the same time. A Crossbar structure consists of N x N cross matrices. When the intersection X, Y) is closed, the data is output from the X input end to the Y output end. The scheduler controls the opening and closing of intersections. Therefore, the speed of the Crossbar structure depends on the speed of the scheduler. The scheduler is the core of the Crossbar switching structure. It collects information about packet queues on each input port in each scheduling time slot, A match is obtained between the input port and the output port through a certain scheduling algorithm, providing a path from the input port to the output port.
There are two main reasons why the Crossbar structure supports high bandwidth: first, the physical connection from the line to the switching structure is now simplified to a point-to-point connection, which allows the connection to run at a very high rate. Semiconductor manufacturers can now use traditional CMOS technology to create a 1 Gbit/s speed point-to-point serial transceiver chip, and can further increase the speed to 4 ~ in the next few years ~ 10 Gbit/s level. The second reason is that its structure can support multiple connections to transmit data at the maximum speed at the same time, which greatly improves the throughput of the entire system. As long as multiple cross nodes are closed at the same time, multiple different ports can transmit data at the same time. In this sense, we say that all crossbars are non-congested internally, because it can support all ports to transmit (or exchange) data at the same time at the maximum rate.
When a data packet passes through the Crossbar, it can be in the form of a fixed-length unit (through the fixed-length splitting of the data packet), or it can be directly used for variable-length switching without splitting. Generally, the high-performance Crossbar switching structure adopts a fixed-length switching mode. Before a data packet enters Crossbar, it is split into cells of fixed length, after these cells are switched, they are organized into the original variable-length packet as they are ).
Both the cross-switch and shared memory can achieve high throughput. Shared Memory is easy to implement and can reach a relatively high throughput, but its scalability is poor. When there are a large number of line interface cards, the performance will be affected. The cross-switch can achieve a relatively high rate and good scalability. However, you need to design a complete scheduling algorithm and use high-speed hardware to implement the scheduler. With the in-depth research on cross-switch scheduling algorithms, many well-performing and simple scheduling algorithms have been designed and implemented. Therefore, high-performance Routers tend to use cross switches as switching structures.
However, the crossover switch and shared memory structure still fall into the category of single-level switching structure. When considering large systems, the single-stage switching structure has two basic problems. First, for small-scale systems, the cost per port is reasonable, but with the expansion of the scale, the cost has also increased rapidly. 2. All single-stage switching structures are technically limited by their dimensions and speed. Once these limits are reached, a Single-Stage Switch cannot add ports or increase the line rate. Because of this, a scalable switching system must adopt a multi-level structure.

2. Multi-level switching structure
The multilevel switching structure is interconnected by multiple switching units. Each switching unit has a complete set of input and output, similar to a common switch, providing an input and output connection. By interconnecting multiple small exchange units, you can create a large and scalable exchange structure. The difference between multi-level structures depends on how the exchange units are interconnected. Typical structures include Benes, Butterfly, and Clos.
Benes networks use square switching units (the same number of input and output ports) for multi-level interconnection. Generally, each level of Level 3 Benes network can use N input/output ports and N switching units to construct Level 4 ). This lattice structure forms N possible paths between each input end and each output end. Benes output can be extended to any odd number.
Although the design of a single-level structure for a small system is relatively simple and the cost is relatively low, it cannot meet the needs of the next generation Internet expansion. The multi-level structure is complex in operation, but can be expanded to hundreds of thousands of ports. This is absolutely necessary for the next generation of Internet Core routing systems. In a multilevel topology, the Benes structure is the best choice, because it has the lowest system complexity, good performance and can meet the scalability requirements.
Iv. fast search of Route tables
As the number of computers on the Internet rapidly increases and users' demand for bandwidth increases, the quick search of Route tables has become the most urgent problem. Traditional software-based routing search strategies, such as tree or hash algorithms, are executed slowly and associated with the route table size. Therefore, these methods can only be used for packet forwarding applications with relatively small performance.
The route table compression technology is used to compress the route table according to specific distribution rules and store it in the high-speed cache of the processor. This greatly improves the query speed. However, the highly optimized and compressed data structure requires more register access and processor cycles to update route tables. This value also increases when the route table increases. When the route table is updated, the entered data packets must be cached or discarded, reducing the performance of the router.
In addition, the uncertainty Based on the software search and Update route table increases the jitter during packet transmission. Therefore, the packet must be cached, resulting in packet loss at a high rate. Therefore, in order to adapt to the development of the network, the ideal packet forwarding solution must not only ensure the data forwarding rate at line speed, in addition, a large enough route table should be provided to meet the needs of next-generation routing devices at a boundary location of 512 K ). At the same time, it also needs to be able to handle long-time burst route table updates with a small update latency. Although the route table is updated several hundred times per second, sudden updates may be much higher.
To solve this problem, the most effective method is to use a dedicated coprocessor combined with the content addressing register CAMContent addressable memory) solution and cache solution to complete fast Route Search or update. However, the core router requires a large forwarding table. Therefore, for the core router, the cache is only an auxiliary method. A large enough cache is required to store the entire forwarding table, and fast algorithms are still required, logical controllers and memories can also be integrated into a single device to shorten Memory Access time.
5. QoS
QoS is short for Quality of Service. The IP protocol has a long delay and is not a fixed value. packet loss leads to discontinuous signals and distortion. Therefore, the application of IP addresses to transmit multimedia information is limited. QoS support for IP networks is the main direction of the next-generation Internet technology development. The degree of QoS supported by routers has also become a major indicator for evaluating the performance of routers. QoS has two main implementation frameworks: IS (Integrated Service) and DiffServ (Differentiated Service ).
IS application Resource Reservation Protocol (RSVP) establishes a sending channel and Reserves Resources before real-time service sending. It notifies a data stream of the IP router of each node that it passes through. It negotiates with the endpoint to reserve resources for this data stream. However, RSVP serves as the target for negotiation of each data stream. When network traffic increases explosively, the number of data streams forwarded by routers increases dramatically, there is no way for a vro to reserve complex resource protocols for each data stream. In addition, when the route is modified due to busy lines or router faults, a relatively time-consuming RSVP process needs to be re-performed.
DiffServ is a decentralized control policy. Its workflow is to obtain a guaranteed service Level for the application data flow of a terminal application device through SLAService Level Agreement) through negotiation with the edge router. Based on the service level, the edge router marks each received packet with a higher level, while the core router only determines the transfer behavior during Forwarding Based on the service level mark of each packet.
MPLS technology can also be used to solve QoS problems.
Vi. MPLS Technology

Multiprotocol Label Switching (MPLS) is an organic combination of ATM Label Switching and IP routing protocols.
Establishes the ing between the IP route table and the label forwarding table of MPLS through mpls ldp protocol, and establishes a label switching path LSP Based on the ing information) -- topology-driven or data-driven. The so-called topological driving mode is to create a label switching path through the MPLS network for each route entry in the route table, the data-driven approach is to create a label exchange path through the MPLS network for the route table entry of the datagram's destination only when the datagram reaches the MPLS network. The MPLS network consists of several LER and LSR. The LER and LSR usually have both IP and MPLS functions. Based on the established tag path, the IP datagram into the MPLS network is marked, forward to the next LSR. The LSR checks the label forwarding table of MPLS and replaces the mark of the datagram with the mark in the label switching path. The LSR continues to be forwarded to the subsequent LSR until it reaches the edge LER of the MPLS network, LER removes the mark of the datagram and forwards the packet down by IP datagram.
The advantage of MPLS is that it converts the completely connectionless packet switching mode in IP technology into a "soft" Packet Switching Mode in MPLS that establishes a labeled switching path based on the LDP protocol, first, the number of times the IP route table is queried through the MPLS network is reduced, instead of the query tag forwarding table, which improves the forwarding efficiency; second, it solves the out-of-order problem of TCP data passing through the IP network. The traffic will pass through the network along the same path and exit the network in the order of going into the network ), this reduces the latency of data sorting at both ends of end-to-end communication, enabling MPLS networks to serve real-time applications.
VII. Optical Router

With the rapid development of the Internet and the explosive growth of Internet data traffic, it is urgent to expand the network capacity in terms of network connections. Synced optical fiber network (SONET) is hard to handle such a huge volume of Internet traffic. Dense Wavelength Division Multiplexing (DWDM) technology emerged, and the backbone network in the future will enter the era of all-optical networks. Because the bandwidth of the whole optical network is huge and the processing speed is high, the router will inevitably develop towards a higher transmission rate and larger transmission bandwidth. In addition, it should also solve the problems of QoS, traffic control, and high price that have plagued people in the past.
Optical router is a good solution. The optical router is a wavelength Selection Device under the control of MPLS protocol and wavelength selection protocol WaRP between the core optical wavelength channels of the network. It achieves Routing Switching and quickly forms a new optical path. Wavelength selection is determined by the internal crossover matrix. a n × N crossover matrix can be used to establish N × N routes at the same time, the wavelength conversion crossover connection connects any wavelength on any optical fiber to any optical fiber with different wavelengths for high flexibility.

At present, both domestic and foreign telecom equipment suppliers TEP and IP equipment suppliers IEP are stepping up the development of a series of optical switching/Optical routing products. Optical router products mainly include Cisco's ONS15900 optical router, Corvis's CoreWave optical router, and Monterey Networks's Monterey 20000 Wavelength Router.