Overview of the chip design process

chip design is divided into front-end design and back-end design, front-end design (also known as logical design) and back-end design (also known as physical design) does not have a uniform strict boundaries, involving the process-related design is the back-end design.

1. Specification Development
Chip specifications, like feature lists, are the design requirements that customers present to chip design companies (known as fabless, fabless), including the specific functional and performance requirements that the chip needs to achieve.

2. Detailed Design
Fabless according to the customer's specifications, come up with design solutions and concrete implementation of the architecture, partition module functions.

3. HDL Code
Using the Hardware Description language (Vhdl,verilog HDL, which is typically used by industry companies), the module functionality is described in code, i.e. the actual hardware circuit function is described in HDL language to form RTL (register transfer level) code.

4. Simulation Verification
Simulation verification is to verify the correctness of the coding design, the standard of inspection is the first step to develop specifications. See if the design accurately meets all requirements in the specification . Specifications are the gold standard for correct design or not, all breaches, does not meet the specification requirements, it will need to re-modify the design and coding. Design and simulation validation is a iterative process until the validation results are fully compliant with the specifications.
Simulation Validation Tool Synopsys VCs, and Cadence's nc-verilog.

5. Logic synthesis ――design Compiler
The simulation verifies the logic synthesis through. The result of the logic synthesis is to translate the HDL code of the design implementation into the gate-level grid table netlist. The combination needs to set the constraints, which you want to synthesize the circuit in the area, timing and other target parameters to achieve the standard. The logic synthesis needs to be based on the specific comprehensive library, the area of the basic standard cell of the gate circuit in different library, the timing parameter is not the same。 Therefore, the selection of integrated library is not the same, the integrated circuit in the timing, the area is different. In general, after the completion of the synthesis need to do the simulation verification (this also known as post-simulation, formerly known as pre-simulation).
The design Compiler of the logic synthesis tool Synopsys.

6. STA
Static Timing Analysis (STA), which is also part of the validation category, is mainly Verify the circuit in time series, check if there is a violation (violation) of the setup times and hold time for the circuit。 This is the basic knowledge of the digital circuit, a register when the two timing violations, there is no way to correctly sample data and output data, so the register-based digital chip function will certainly be problematic.
The STA tool has Synopsys prime time.

7. Formal verification
This is also a validation category, it is the function (STA is the time series) on the Integrated network table validation. commonly used is the equivalence check method, with the HDL design after functional verification as a reference, compared with the Integrated network table function, they are functionally equivalent。 This is done to ensure that the circuit functions described in the original HDL are not changed during the logic synthesis process.
The formal validation tool has Synopsys formality.

the front-end design process is temporarily written here. From the design level, the result of the front-end design is to obtain the chip gate-level grid circuit.

Backend Design Flow:

1. DFT
Design for test, testability. The inside of the chip often comes with a test circuit, and the purpose of DFT is to consider future tests when designing. A common method of DFT is to insert a scan chain in the design, changing a non-scanning unit (such as a register) into a scanning unit。 About DFT, some books have detailed introduction, the control picture is good to understand a little.
DFT Compiler for DFT tool Synopsys

2. Layout planning (Floorplan)
Layout planning is The Macro unit module is placed on the chip to determine the placement of various functional circuits in general, such as IP module, ram,i/o pin, etc.。 Layout planning can directly affect the final area of the chip.
Tools for Synopsys's Astro

3. CTS
Clock Tree Synthesis, clock tree Synthesis, the simple point is that the clock wiring。 due to the global command of the clock signal in the digital chip, its distribution should be symmetrical to the various register units, so that the clock from the same clock source to each register, the clock delay difference is minimal。 This is why the clock signal needs to be routed separately.
CTS tool, Synopsys physical Compiler

4. Cabling (Place & Route)
The wiring here is General Signal Wiring, including the route between various standard units (basic logic gate Circuit). For example, we usually hear the 0.13um process, or 90nm process, in fact, here the metal wiring can reach the minimum width, from the microscopic point of view is the MOS pipe channel length.
Astro of Tool Synopsys

5. Parasitic parameter Extraction
Due to the resistance of the wire itself, the mutual inductance between the adjacent conductors, the coupling capacitance inside the chip generates signal noise, crosstalk and reflection. These effects result in signal integrity problems, resulting in signal voltage fluctuations and changes, which can cause signal distortion errors if they are serious. extraction of parasitic parameters for analysis and verification, analysis of signal integrityThe problem is very important.
STAR-RCXT of Tool Synopsys

6. Physical verification of the layout
The physical layout of the complete wiring to verify the function and timing, validation of a lot of projects, such as LVS (Layout Vs Schematic) Verification, simply speaking, is the layout and logic synthesis of the gate-level circuit comparison verification; DRC (Design Rule Checking): Design rules check, check the line spacing, line width and so on to meet the process requirements, ERC (electrical rule Checking): Electrical rules Check, check the short circuit and open and other electrical rules violation;
Tools for Synopsys's Hercules

the actual back-end process also includes circuit power analysis, as well as the DFM (manufacturability design) problem that arises as the manufacturing process progresses, not to mention here.

Physical layout verification is completed in the entire chip design phase, the following is the chip manufacturing. The physical layout is presented to the chip foundry (called Foundry) in the GDS II file format to make the actual circuit on the wafer wafer, and then package and test it to get the chip we actually see.

Links: http://www.zhihu.com/question/28322269/answer/42048070

Overview of the chip design process