Principles and Performance Comparison of ARM chips

General principles of ARM chip selection:

1. Function USB network serial port LCD display

2. Performance, power consumption, and speed

3. Price

4. Operating System Support

5. familiarity and development resources

6. stable supply of General chips for large manufacturers

ARM Series		MMU/MPU	Structure	Power Consumption mW/MHz	Speed MIPS/MHz	Clock speed MHz	Application fields
ARM7		Without	Level 3 Assembly Line Von noriman Structure	0.28	0.9	20-133	Industrial Products
ARM9.		MMU	Level 5 Assembly Line Harvard Structure	0.7	1.1	100-233	Consumption, medical care, Industry
Arm10e		MMU MPU	Level 6 Assembly Line V5 Architecture	1000	1.25	300-700	Wireless devices and digital consumer goods
Arm11		MMU	8-level Assembly Line V6 Architecture	0.4		350-500	Advantages in consumer, network, and multimedia processing
Cortex	Cortex-	MMU	V7 Architecture	<300	2.0	600-1000	Applications, consumption, and wireless products
	Cortex-R	MMU	V7 Architecture	0.27	1.62	300	Real-time Control Automotive Electronics, networks, and Imaging Systems
	Cortex-m	MPU	Level 3 Assembly Line V7 Architecture	0.19	1.25	100	Microcontroller, vehicle body system, network device
Securcore		MPU	Level 5 Assembly Line	-	--	--	Security, e-commerce, and online banking

MMU: Storage Management Unit

MPU: storage protection unit,

Compare items	ARM7	Cortex-M3
Architecture	Armv4t (von noriman) When commands are shared with the data bus, bottlenecks may occur.	ARMv7-M (Harvard) Separate commands from the data bus without bottlenecks
Instruction Set	32-bit arm instruction + 16-bit thumb instruction Status switching is required between two sets of commands.	Thumb/thumb-2 instruction set 16-bit and 32-bit Command can be directly mixed-write without status Switching
Assembly Line	If a third-level pipeline is transferred, the pipeline needs to be refreshed, causing heavy losses.	3-level pipeline + branch prediction when there is a transfer, the pipeline does not need to be refreshed, almost no loss
Performance	0.95 dmips/MHz (arm Mode)	1.25 dmips/MHz
Power Consumption	0.28 mW/MHz	0.19 mW/MHz
Low Power Consumption Mode	None	Built-in sleep mode
Area	62mm2 (kernel only)	86mm2 (kernel + peripherals)
Interrupted	There are too few normal IRQ interruptions and fast FIQ interruptions, and a large number of peripherals have to reuse the interrupt.	Unshielded NMI + 1-2 40 physical interruptions Each peripheral can have an exclusive interruption with high efficiency.
Interruption Delay	24-42 clock cycles, slow	12 clock cycles, up to 6
Interrupt pressure Stack	Manual software stack pressure, long code and low efficiency	Automatic hardware pressure stack, no code and High Efficiency
Storage Protection	None	8-segment memory Protection Unit (MPU)
Kernel register	Registers are divided into multiple groups, complex structures, and many occupied cores.	Registers are not grouped (except SP), and the structure is simple.
Working Mode	7 working modes, complicated	Only the thread mode and processing mode are available, which is simple.
Multiplication and division commands	Multi-period multiplication command, no division command	Single-cycle multiplication command, 2-12-cycle division command
Bit operation	The unaccessed peripheral register must be divided into three steps: "Read-Modify-write ".	Advanced bit-band operating technology that allows you to directly access a value of a peripheral register
System cycle timing	None	Built-in system timer, facilitating OS migration