The process needs to be prepared before switching, where kernel processes and user processes are handled differently in the switch address space, mainly because the kernel process uses only the kernel address space, and the kernel address space for Linux is fixed, but the user process is different. While the kernel borrows the user's address space, the page table information in the Mm_struct is cached in the TLB, and the refresh problem must be consistent, recommending two articles that are well written and very clear about the problem.
Lazy mode of Linux TLB refresh
http://blog.csdn.net/Henzox/article/details/41963271
This article mainly describes theSmpOn the processor, eachCpuHave their ownTlb, in aCpuWhen borrowing the memory space of a user process, this user process may be in anotherCpuCan cause changes in the memory space of the process,Tlb data will fail, in order to maintain consistency, will refer to this memory space cpu send ipi< The span lang= "ZH-CN" > message informs it to refresh the corresponding tlb entries. task_struct record cpu to its mm_struct The information referenced is stored in cpu_vm_mask32 cpu information logging, Tlbstate_lazy mode, cpu processing ipi message, the cpu corresponding bit mask cleared, not refreshed tlb ipi message will not be sent back to their own here.
"Try to summarize memory barrier (classic)"
http://blog.csdn.net/zhangxinrun/article/details/5843632
This article mainly talk about the modern CPU in order execution and compile optimization, and JIT technology so that the CPU in the actual execution of instructions may not be as you write code when the serial execution, the role of adding memory wall barrier is to prevent GCC compiler optimization of the code, the overall implementation of the main function is to ensure that the memory wall before the write operation is done, the memory wall after the read code from memory re-read data.
The memory wall barrier is implemented on the x86 by the lock bus, which invalidates all CPU caches of data for the instruction operations involved in lock , and the lock Will cause the current CPU to write its cache to memory, through (bus-watching) technology, the other CPU will make the cache with the corresponding data fail, that is, the next access must be accessed from within. Cache Consistency is maintained through the MESI protocol.
Switch source of register information
1 #defineSwitch_to (prev,next,last) do {2Asmvolatile(3 "PUSHL%%esi\n\t" 4 "PUSHL%%edi\n\t" 5 "PUSHL%%ebp\n\t" 6 "MOVL%%esp,%0\n\t" /*Save ESP*/ 7 "MOVL%3,%%esp\n\t" /*Restore ESP*/ 8 "MOVL $1f,%1\n\t" /*Save EIP*/ 9 "PUSHL%4\n\t" /*Restore EIP*/ Ten "jmp __switch_to\n" One "1:\t" A "popl%%ebp\n\t" - "popl%%edi\n\t" - "popl%%esi\n\t" the:"=m"(PREV->THREAD.ESP),"=m"(prev->Thread.eip), - "=b"(last) -:"m"(NEXT->THREAD.ESP),"m"(next->Thread.eip), - "a"(prev),"D"(next), + "b"(prev)); -} while(0)
esi,edi,< Span lang= "en-US" >ebp,esp deposit task_ Struct1: Beginning as eip save, the next time you find a process is scheduled, ret After returning from here to start execution.
Loading the new process of ESP, the EIP Stack, this eip actually corresponds to the last time they were scheduled to leave the storage of 1: The location, so the last ret Return from here to start execution, restore EBP, edi,esi, full recovery process.
__switch_to has a fastcall tag, the function's parameters are taken in eax and edx , which corresponds to prev and next.
__switch_to Save prev FPU,fs,GS segment, empty the possible IO permissions bitmap bitmap, will Next process the kernel stack pointer,FS,GS, possible debug register information, and set its IO permissions to bitmap bitmap.
Next is the memory management, or very fast.
Process Switch switch_to () comment