Q24plus openat SPI access

 

It took more than half a month to figure out the SPI. In general, the road was not smooth, but the goal was finally achieved.

Q24plus provides a three-line SPI (I/O/CLK/EN). Io can be automatically controlled by the bus into the input or output status, and enabled by the function. The clock is configured according to the configuration.

, A maximum of 13 MHz and a minimum of 812.5 kHz. Supports SPI Mode 0 and Mode 3.

I initially planned to use an external SD card, but after such a long period of debugging, I gave up this idea for the moment. After a while, I will go back and do research on SD.

Generally, the SPI storage chip sends data along the rising edge and reads data along the falling edge. However, due to the SPI function provided by Wavecom, I choose to send and receive data along the rising edge, but this will cause

The data reception is unstable. Therefore, the communication clock cannot be too fast and it will be misplaced if it is too fast.

A struct definition for Spi/I2C operations:
Typedef struct
{
U32 address;
U32 opcode;
U8 opcodelength;
U8 addresslength;
U8 accesssize; (reserved for future products)
} Adl_busaccess

Many people do not know how to use this structure, and the SDK is not detailed. I searched a lot of information and asked a lot of people. I finally figured it out. I will give it to you for free:
Address: 32-bit address
Opcode: operation code
Opcodelength: operation code length
Addresslength: Address Length
Accesssize: This version is not required

Whether we are using adl_busread or adl_buswrite, the data in this struct will be sent as the first one, and the following parameters will be sent in the second clock cycle

During the sending period, the clock will remain valid and will not pause. At the same time, the enabling rate will remain low.

S8 adl_busread (u8 handle, adl_busaccess_t * paccessmode, u32 datalen, void * data );

Returned value: whether the read is successful. In fact, whether the read is successful or not is for your configuration. The final data returned by the chip is in data.
Execution sequence:

Initialize clock
Enable
Send the operation code. The length of the operation code is specified according to opcodelength. Please note that the operation code is initiated from a high position and the data type is u32. Therefore, if it is less than 32 characters,

Please take a look. If the operation code length is set to 0, it will not be sent here;
The Sending address. The length of an address is specified by addresslength. The sending method is the same as the operation code.

According to the length of the datalen, The datalen x eight clock periods are sent, and the read data is stored in the memory pointed to by the data.

Now, the read operation is complete.

S8 adl_buswrite (u8 handle, adl_busaccess_t * paccessmode, u32 datalen, void * data );

Return Value: whether the write operation is successful. In fact, whether the operation is successful or not is for your configuration.
Execution sequence:

Initialize clock
Enable
Send the operation code. The length of the operation code is specified according to opcodelength. Please note that the operation code is initiated from a high position and the data type is u32. Therefore, if it is less than 32 characters,

Please take a look. If the operation code length is set to 0, it will not be sent here;
The Sending address. The length of an address is specified by addresslength. The sending method is the same as the operation code.

Based on the length of datalen, datalen x eight clock cycles are sent. At the same time, the data pointing to the data is output through Io, with one output per clock cycle.

Now, the write operation is complete.

I have now received a 32 Mbit flash, and all the read and write operations have been smoothly tuned.

The Study of q24plus will come to an end. The module has no new functions to deal with. At the same time, due to the reasons of this product itself, there is not much value for further development.

The research target is q2686. This module brings us a new experience.
Arm9-processor, two independent 4-wire SPI, one independent I2C, up to 3.4 Mbit, up to 100 gpio pins, the most important thing is that 3G is pin2pin compatible.