"Design Experience" 2, Chipscope use tutorial

First, software and hardware platform

Software platform:

Operating system: Windows 8.1

Development Kit: ISE14.7

Hardware platform:

FPGA model: xc6s45x-csg324

Ii. introduction of Chipscope

Chipscope is a tool that Xilinx offers to validate FPGA designs. Its essence is a virtual logic analyzer that can invoke logical resources inside the FPGA to fetch and analyze each variable in the code. Unlike some other FPGA simulation tools such as Modelsim, Chipscope can directly reflect the implementation of the Code on the actual hardware, so that it can more effectively locate the problem in the design.

Iii. Target Tasks

This article will take a 4-bit counter as an example to show you how to use Chipscope to verify the function of this counter. For a 4-bit counter, the lowest bit of the counter bit0 is the clock signal 2, bit1 is the clock signal 4, BIT2 is the clock signal 8, the highest bit bit3 is the clock signal 16. Next, we use Chipscope to verify the correctness of this logic.

I have four LEDs and four buttons on my board, so I'm going to bind the counter's 4-bit to four LEDs respectively, and then design an asynchronous reset button in logic to reset the counter, and design this asynchronous reset to set the initial trigger condition. This is explained in more detail later.

Four, the code to be tested

ModuleLed_top (inputI_CLK,inputI_rst_n,Output  Reg[3:0] o_led_out);  always@(PosedgeI_clkor Negedgei_rst_n)begin       if(!i_rst_n) O_led_out<=4'D0;       ElseO_led_out<= O_led_out +1'B1;End  Endmodule

Write the code you want to test and add a physical constraint file to bind the PIN, the constraint file on my development Board is as follows

# #NET I_CLK LOC= V10 | Tnm_net = Sys_clk_pin | Iostandard ="LVCMOS33"; Timespec Ts_sys_clk_pin= PERIOD Sys_clk_pin50000khz;### #NET i_rst_n LOC= N4 | Iostandard ="LVCMOS15"; # # SW2 pushbutton######### #LED Pin define#################### #NET o_led_out<0> LOC = V5 | Iostandard ="LVCMOS33"; # # Led1net O_led_out<1> LOC = R3 | Iostandard ="LVCMOS33"; # # Led2net O_led_out<2> LOC = T3 | Iostandard ="LVCMOS33"; # # Led3net O_led_out<3> LOC = T4 | Iostandard ="LVCMOS33"; # # LED4

V. Chipscope use of the complete process

1. Build a new project in ISE14.7 using the code and constraint files above. Then click on synthesize-xst to synthesize the whole project again.

2. Select the top-level module name Led_top, then right-click the new source option and select the second Chipscope Definition and Connection file option in the Popup New Source wizard interface. and take the name chipscope_led (name can be taken casually), and then click Next

3. Click Next to click Finish in the popup dialog box.

4, Finish Click after completion, and so on for a period of time, the level of the project directory is more than a suffix. CDC chipscope file

5, double-click the CHIPSCOPE_LED.CDC file, will pop up the following interface, using the default settings to ensure that the use Srls and uses RPMs is selected

The use Srls (SRL = shift Register LUT) option allows the compiler to replace the trigger (flip flops) and multiplier with the lookup table (Shift register LUTs) of the shift register, thus effectively reducing the internal FPGA resources. Improved Chipscope performance

Use RPMs (RPM = relationally Placed Macros) contains rloc constraints, and Rloc defines the order and structure of the potential design primitives. Use RPMs make compiler with Fmap,hmap,rom,ram and other related macro modules, make logical block layout more reasonable, can effectively improve speed and performance, and save FPGA resources

6, the previous step selected and click Next after the following interface, the interface remains the default settings

7. Continue clicking next to pop up the following screen. In this interface select the number of trigger ports (Trigger Ports) and their respective widths (Trigger width),

Description

A, it is recommended that the trigger width (Trigger width) is selected as the maximum value of 256, after the signal is added after the return to change the total width of the signal. This is because in a more complex design, you do not know in advance how many signals, so you have to grasp the signal is set up later in the back to modify this parameter is a better choice.

b, there are 6 types of Match type, each supported value type and function see the following table

Match Type	Bit Values	Functions
Basic	0,1,x	=,<>
Basic w/edges	0,1,x,r,f,b,n	=,<>
Extended	0,1,x	=,<>,>,>=,<,<=
Extended w/edges	0,1,x,r,f,b,n	=,<>,>,>=,<,<=
Range	0,1,x	=,<>,>,>=,<,<=,in Range,not in range
Range w/edges	0,1,x,r,f,b,n	=,<>,>,>=,<,<=,in Range,not in range

The meanings of the parameters in the table are as follows:

Parameters	Meaning
0	Low Level
1	High level
X	Indeterminate value
R	Rising Edge (Rising)
F	Falling Edge (Falling)
B	Dual Edge (Both edge)
N	Non-edge (no edge)
=	Equals
<>	Not equal to
<	Less than
<=	Less than or equal
>	Greater than
>=	Greater than or equal
In range	Within a range
Not in range	Not within a range

Because this example is relatively simple, match type is selected as basic.

C, the Enable Trigger Sequencer option specifies the number of levels that trigger the queue, which remains the default. The structure diagram of the triggering queue is shown

D, enable Storage qualification option to filter the captured data by user-defined conditions, this option generally makes it the default choice

8, click Next to enter the Capture Parameter tab, this page in this example to keep the default parameters can be

Description

A, data depth refers to the number of data sampled when the trigger condition is met. The larger the value is, the more information you get, but the more resources you have inside the FPGA. If you want to crawl the UART and IIC data, because the UART and IIC protocol transmission speed is slow, so this value must be set to a larger point to see more information, and for the SPI such a faster transfer protocol, this value can be set smaller.

b, the data same as trigger option means that the signal you are grabbing can either trigger the signal or act as a data signal. Here is a suggestion, for the inout signal (bidirectional signal), it is best to choose only as a data signal, not as a trigger signal.

9. Click Next to enter the Net Connections Options page

10. Double-click the Red Clock port option to connect the clock signal in the order of 1, 2, 3 in the Popup interface

11, even a good clock signal after clicking OK, return to the net connections interface, found that the clock port has been changed from red to black, indicating that the timing is successful, then double-click the Red Trigger PORTS, in the popup interface to set the signal to grab

12, to grab the signal set after the click OK to return to the Net Connections Options page, found that trigger ports is still red, this is because we previously set the total width of the capture signal is 256, and here we only grabbed 5 signals, so we need to return trigger Parameter page set trigger width to 5

13, set the correct trigger width after the return to the Net Connections Options page can be found trigger ports has become black, and then click Return to Project Navigator

14. In the Save Project dialog box that pops up, select Yes

The setup process for the entire. CDC file is now complete.

15. Then double-click Generate programming file to generate bit files

16. Connect the JTAG line of the Development Board and Power on. Double-click the Analyze Design Using chipscope to open the Chipscope interface as shown below

17, if the JTAG connection is normal, the following window will pop up, this window indicates that the development Board was found to use the FPGA model xc6slx45

18, click OK, the upper left corner of the p tag turned green, Jtag chain more out of the FPGA model this label

19. Left Click to select dev:0 MyDevice0 (xc6slx45), then right-click the menu bar and select Configure in the menu bar.

20. Tick the import design-level CDC file and auto-create buses two options in the popup interface

21, click on the ok,bit file is downloaded to the Development Board, and then enter the following interface

22. Double-click Trigger setup and waveform to open the settings triggered window and the waveform window respectively.

The depth in the trigger window is where we set the depth of data to fetch in the. CDC file, position this parameter is 0 by default, but it is recommended to set an offset, where I set the 100, which represents the 100 data that the trigger condition satisfies before the trigger condition satisfies the 924 (1024-100) The data is displayed in the waveform window, so that we can capture a portion of the information before the trigger, which is more helpful for locating the problem. Storage qualification This parameter is only available after the. CDC file has been checked for the Enable Storage qualification option, and the default all Data is generally selected.

The Waveform window is the window that displays the waveform to be crawled, which is not started, so it appears empty.

23. Click on the No. 1th icon in the upper right corner to enlarge the trigger Setup window and set the trigger condition to I_rst_n R (R for rising edge), then click on the 3rd icon to enter the waiting trigger state.

24. Wait for Trigger status

25, click on the Development Board i_rst_n Signal binding button, so that the trigger conditions to meet the waveform window appeared to catch the waveform

The red T-ruler represents the start position of the trigger, its position cannot be moved, the green O and blue x are two movable rulers, both the absolute position and the difference are displayed in the lower right corner of the waveform window, sometimes you need to measure the difference of two key points can drag the two rulers to directly draw the results

26, with the mouse in the waveform window to draw a rectangular box to enlarge the waveform window, you can see more waveform details

27, if I want to let o_led_out for 4 ' b0010, then modify the trigger condition as shown, then click the Trigger button

28, because we set the o_led_out has been in self-increment, so do not need to press the button, such as O_led_out for 4 ' b0010 trigger conditions can be triggered, after triggering the waveform as shown

It is obvious that the trigger position is in the position of O_led_out 4 ' b0010, and the same as previously set.

29. If you want to see the waveform of each bit of the O_led_out bus, click on the small icon in front of the signal name to expand

30. If you want to see the analog waveform of the O_led_out bus, then you can double-click the Buses Plot tab and select the O_led_out bus in the popup interface.

30, more functions we have time to try a lot. This chipscope tutorial is complete.

Vi. How to prevent the signal from being optimized

In a complex design, we tend to catch a large number of signals, and ISE14.7 compile the code will be some of the same logic to optimize the signal, which will lead us to choose the signal when we do not find the signal to grab, in response to this situation to provide you with two solutions.

Method One:

1. Add (*keep = "TRUE") before all the signals you want to crawl

(*keep = "TRUE" *) reg [3:0] r_cnt;

2, select Synthesize-xst, right mouse button in the popup menu bar Select Process Properties ...

3, in the Pop-up window select-keep_hierarchy for soft, (yes and soft the difference I am not clear, but I am accustomed to choose soft, I hope that a netizen can provide answers and sources, thank you)

4, set up after the re-synthesis, and then re-select the signal to crawl in the. CDC

Method Two:

The above method according to my experience does not have 100% guarantee signal not to be synthesized, so there is another way is to write a redundant logic to the signal and then assign a value to the output, and the output to the top layer bound to a free pin, this case my method is:

Suppose the signal to be crawled is (*keep = "TRUE" *) reg [3:0] r_cnt;

1, the definition of 1 output signal o_test;

Output o_test;

2, the signal to be captured or then assigned to O_test

Assign o_test = | r_cnt;

R_cnt "|" in front of the Each bit of the r_cnt is indicated by the phase or

3. Bring the o_test to the top and assign a spare pin in the constraint file

Through this way of increasing redundancy logic, the r_cnt signal is generally not synthesized, I will use the first method in my usual use, if I find the first method or the key signal I want to see the combination of the words to use the second method.

Seven, the use of a case of the ILA nucleus of the way to grasp the signal

In addition to using the. cdc file to fetch the signal, there is another way to take the timing of the signal in a way that uses the ILA kernel as a sample. The detailed operating procedure for this approach is as follows:

1. Add a new icon IP core

2, in general, to keep all the parameters by default.

3. Add a ILA IP core

4, on the first page set up the relevant parameters, the meaning of these parameters of the kernel. The parameters in the CDC file are exactly the same, and there's no longer much to explain

5, the second page is mainly set to grasp the width of the signal, refers to the note is here can set a big point does not matter, because this method does not require the signal width and the number of signals to be captured exactly the same

6. After generating this two IP cores, instantiate the two IP cores into the code

ModuleLed_top (inputI_CLK,inputI_rst_n,Output  Reg[3:0] o_led_out);  always@(PosedgeI_clkor Negedgei_rst_n)beginif(!i_rst_n) O_led_out<=4'D0;ElseO_led_out<= O_led_out +1'B1;End    Wire[ *:0] CONTROL0; Wire[7:0] Trig;icon icon_debug (. CONTROL0 (CONTROL0)//INOUT BUS [35:0]); Ila ila_debug (. CONTROL (CONTROL0),//INOUT BUS [35:0]. CLK (I_CLK),//inch. TRIG0 (TRIG)//In BUS [7:0]); Assigntrig[0]=I_rst_n;Assigntrig[4:1]=o_led_out; Endmodule

The next step is to generate a bit file and grab the signal with Chipscope, just like in the previous method.

The difference between this method and the previous method is that this method can only crawl a. v file in the signal, and the speed of the generation of IP cores is slow, into the chipscope will need to modify the name of the port, it is a waste of time; The advantage is that 100% guaranteed to catch the signal, So for the less complex logic of the single-file code can be used this way. But I personally prefer to use the. cdc file to capture the signal.

Viii. Summary

1, using ILA Logic Analyzer to capture the signal there are two ways:. CDC file Mode (recommended) and instantiate ILA kernel mode

2. There are two ways to prevent the signal from being optimized in the CDC file: Keep_hierarchy selected as soft, adding redundant logic

Welcome to my public number: the Zen of FPGA

"Design Experience" 2, Chipscope use tutorial