"FPGA full Step---Practical Walkthrough" the eighth chapter of the program structure format description

The first part that must be written in the program is the Module modules section, as shown in the overall schema 8.1.

Figure 8.1 Overall Program architecture

First of all to declare the module name, after module name, it is best to create the module to implement the function to name this module, because it is convenient to find the function of this module in the lookup, at a glance. All input and output signals should be listed in the box immediately after the box is written. As a whole module, all things appear module part must add Endmodule to calculate complete, this is a complete module.

In the input signal, there are two signals must be added to, is the clock signal and reset signal, to achieve the overall design controllable, global clock signal and reset signal must be added. After declaring the parentheses on the input and output signal columns, it is also necessary to re-declare in the module which is the input signal, which is the output signal, which has 124 lines to 128 lines of declaration. Some of the variables used in the Always statement need to be defined as the Reg type, which is the register type, which can be employed in always, and the wire type cannot be used in a never statement.

When we look at code written by someone else, we often see a structure similar to the one shown in lines 130 to 153, what's going on? What is this about? This is going to take advantage of the combination logic and timing logic in our digital knowledge, which requires time-series logic in the case where the variables are stored, and the combinational logic can only output data, but it cannot be stored. Of course, the combination logic is the level trigger, and the timing logic is the clock along the trigger. So 130 rows to 153 lines build a huge latch that forms a sequential logic circuit. For a sensitive variable inside a 130-line parenthesis, the change will cause the entire always statement to update. Where Rst_n (this is the reset signal, can be defined according to their own habits.) is also defined as an edge-sensitive variable, but there is rst_n in the inside of the always statement, which is why? A signal if it is a clock signal, then must not appear in the Always statement, the visible rst_n is not a clock signal. So will the integrated device think that rst_n is a clock signal?

For the Verilog design of the edge-triggered timing module, the following rules are available:

(1) If the sensitive variable is defined as a clock signal, do not re-appear in the Always statement.

(2) If a signal is defined as a level-sensitive asynchronous control signal relative to the clock, in addition to being listed in the sensitive variable table, its logical behavior is indicated in the always statement.

(3) If a signal is a synchronous control signal relative to the clock, it cannot appear in the sensitive variable table.

By the above program structure, specifying an if statement for rst_n causes all variables that fail to enter the sensitive signal to be synchronized relative to the clock. It can be seen that this is the timing or composition logic independent of the master clock, which is the second case.

(4) Mixed signals are not allowed in the sensitive variable table.

[Email protected] (Posedge CLK or RSTN) or [email protected] (Posedge CLK or Negedge rstn or a)

The above structures are not allowed, and in the synthesis there will be a bilateral error along the sensitive signal.

(5) Not allowed to appear in the sensitive list except the clock and the asynchronous control signal other than the signal, the general logic control signal is not allowed to appear in the sensitive list, [email protected] (Posedge CLK or Negedge a)

Where a has the same effect as RSTN, but a cannot be used for other logical behaviors. such as Q = A & B;

Visible Verilog describes the rules that are more dependent on the syntax of the sensitive timing circuit

If the asynchronous control signal Rst_n is judged in the IF statement, then the data is initialized, after initialization is done in other conditions, else if......else, wherein the begin....end is for the multi-step execution of the program in the conditional statement, the build into a whole, belongs to the else if statement or else statement.

155 Rows to 157 rows are assigned to the output signal used by the user. The above is for the establishment of a single module, if only to establish a single module, in the establishment of the project must be the name of the module and the project name is consistent, 8.2, otherwise it will be wrong. For multiple modules to build, we need to recommend a top-level module, and then the various sub-modules to connect, then use the wire variable, 8.3, pay attention to the wire type of LED signal, play the role of connecting the various modules. Figure 8.4 is the RTL view portion of multiple modules, and you can see the effect of the wire.

Figure 8.2 Naming a single module

Figure 8.3 Multiple module naming

Figure 8.4 RTL View

testbench Format Description

When the logical part is finished, the logic program needs to be simulated, then the emulator needs to be written.

' Timescale 1 NS/1 NS

Module LED_SOURCE_TST ();

//----------------------------------------------

-----------Description of input signal--------

Reg CLK;

Reg Rst_n;

CLK and Rst_n are global clock and reset signals

//----------------------------------------------

-----------Description of output signal--------

Wire [3:0] led_out;

Wire .....

Wire .....

In Modelsim emulation, input in the. v file is used in the Modelsim with a reg type, such as CLK is input,

The above Modelsim is used in the output of the reg,.v file, that is, outputs, in the Modelsim is a wire, this should bear in mind

//----------------------------------------------

-----------Description of each module-------------------------

Led_source

#(. Led_width (4))

I1 (

Port map-connection between master ports and Signals/registers

. CLK (CLK),

. Cnt1 (Cnt1),

. Flag_cnt1 (Flag_cnt1),

. Led_out (Led_out),

. Led_out_cnt1 (Led_out_cnt1),

. Rst_n (Rst_n)

);

This is part of the module declaration section in the. v file that was created. Led_source is the module name in the. v File

//------------------------------

Generate clock

Localparam PERIOD = 20; 50MHz

Initial

Begin

CLK = 0;

Forever # (PERIOD/2) CLK = ~CLK;

End

The above section is a simulation of the CLK signal;

//------------------------------

Task Reset

Task Task_reset;

Begin

Rst_n = 0;

Repeat (2) @ (Negedge CLK);

Rst_n = 1;

End

Endtask

The above section is for the reset signal, i.e. rst_n.

At first, it also assigns the initial value rst_n = 0; then executes the command repeatedly with repeat;

Initial

Begin

$monitor ($time, "led_value =%04b\n", led_out); Just test the changing of Led_out//value

Task_reset;

End

This part of the above is a call to the above task module and simulation of the input signal, of course, this part does not use the//user input signal.

Endmodule

Figure 8.5 is the emulator for the key, the input is also defined as a task, and then in 101 rows to 105 lines to make a call to the mission, clear.

Figure 8.5 Invocation of the input signal

"FPGA full Step---Practical Walkthrough" the eighth chapter of the program structure format description