Realization of digital clock realization and dynamic adjustable and alarm function

RTL structure of the design

Processing module to achieve mode switching and counting, 4-bit digital tube decoding after the 595control module control digital tube flashing and half-second flashing, 595function module 16-bit serial output to 595 drive Digital tube display

Module Jishu
(
Input CLK,
Input Rst_n,
Output [3:0] Row_data,
input [3:0] Col_data,
Output Alarm_beep,
Output[3:0]seg_flash_data,
Output Flag_1s,
Output [15:0]bcd_seg_display_num,
Input mode_in
);
Wire [3:0]key_value;
Juzhen Key_input
(
. CLK (CLK),
. Rst_n (Rst_n),
. Col_data (Col_data),
. Row_data (Row_data),
. Key_value (Key_value),
. Key_flag_r0 (KEY_FLAG1),
. Key_flag (Key_flag)
);
Parameter t_half_s=12500000;
Parameter t_1s=25000000;

reg [24:0]count1;
Reg Flag_1s_r;
[Email protected] (Posedge CLK or Negedge rst_n)
Begin
if (!rst_n)
Begin count1<=0; Flag_1s_r <= 0; End
else if (count1 = = t_half_s)
Begin
Count1 <= count1 + 1 ' B1;
Flag_1s_r <=~ Flag_1s_r;
End
else if (count1 = = t_1s)
Begin
count1<=0;
Flag_1s_r <=~ Flag_1s_r;
End
Else
Count1 <= count1 + 1 ' B1;

End
Assign flag_1s = Flag_1s_r;
Wire key_in;
Debounce Xiaodou

(
. CLK (CLK),
. Rst_n (Rst_n),
. Key_n (mode_in),
. Key_pulse (key_in)
);

reg [3:0]bcd_sec_one_cnt;
reg [3:0]bcd_min_one_cnt;
reg [3:0]bcd_hour_one_cnt;
reg [3:0]bcd_sec_ten_cnt;
reg [3:0]bcd_min_ten_cnt;
reg [3:0]bcd_hour_ten_cnt;
REG[3:0] Seg_flash_data_r;
Wire [15:0] bcd_seg_display_num;
REG[2:0] mode;
reg [15:0] bcd_seg_display_num_r;

Always @ (Posedge CLK or Negedge rst_n)
Begin
if (!rst_n) begin Mode<=0;end
Else
Begin if (key_in==1) if (mode = = 3 ' b110) mode <= 3 ' b000;
else mode <= mode + 1 ' B1;
End
End

Always @ (Posedge CLK or Negedge rst_n)
if (!rst_n) begin Bcd_sec_one_cnt<=0;bcd_sec_ten_cnt<=0;bcd_min_one_cnt<=0;bcd_min_ten_cnt<=0;bcd_ Hour_one_cnt<=0;bcd_hour_ten_cnt<=0;seg_flash_data_r<=4 ' B0000;end
Else
Begin
Case (Mode)
0:begin seg_flash_data_r<=4 ' b0000;
Bcd_seg_display_num_r[15:0] <= {bcd_min_ten_cnt,bcd_min_one_cnt,bcd_sec_ten_cnt,bcd_sec_one_cnt};
if (count1 = = t_1s) begin if (bcd_sec_one_cnt==9)
Begin bcd_sec_one_cnt<=0; if (bcd_sec_ten_cnt==5)
Begin Bcd_sec_ten_cnt<=0;if (bcd_min_one_cnt==9)
Begin Bcd_min_one_cnt<=0;if (bcd_min_ten_cnt==5)
Begin BCD_MIN_TEN_CNT&LT;=0;IF (bcd_hour_ten_cnt==2&&bcd_hour_one_cnt==3) Begin BCD_HOUR_TEN_CNT&LT;=0;BCD _hour_one_cnt<=0;end
else if (bcd_hour_one_cnt==9) begin Bcd_hour_one_cnt<=0;bcd_hour_ten_cnt<=bcd_hour_ten_cnt+1;end

else bcd_hour_one_cnt<=bcd_hour_one_cnt+1;
End
else Bcd_min_ten_cnt<=bcd_min_ten_cnt+1;end
else Bcd_min_one_cnt<=bcd_min_one_cnt+1;end
else Bcd_sec_ten_cnt<=bcd_sec_ten_cnt+1;end
else Bcd_sec_one_cnt<=bcd_sec_one_cnt+1;end End
/* 1:begin seg_flash_data_r <= 4 ' b0001;
if (key_value==6&key_flag==1) seg_flash_data_r[3:0] <= {seg_flash_data_r[2:0],seg_flash_data_r[3]}; Move left to adjust the bit
if (key_value==14&key_flag==1) seg_flash_data_r[3:0] <= {seg_flash_data_r[0],seg_flash_data_r[3:1]};// Move right to adjust the bit
Bcd_seg_display_num_r[15:0] <= {bcd_min_ten_cnt,bcd_min_one_cnt,bcd_sec_ten_cnt,bcd_sec_one_cnt}; Seconds to adjust the display interface
if (seg_flash_data_r[0]==1&key_value==13&key_flag==1) begin if (bcd_sec_one_cnt==9) bcd_sec_one_cnt<=0; else Bcd_sec_one_cnt<=bcd_sec_one_cnt+1;end
if (seg_flash_data_r[1]==1&key_value==12&key_flag==1) begin if (bcd_sec_ten_cnt==5) bcd_sec_ten_cnt<=0; else Bcd_sec_ten_cnt<=bcd_sec_ten_cnt+1;end
if (seg_flash_data_r[2]==1&key_value==9&key_flag==1) begin if (bcd_min_one_cnt==9) bcd_min_one_cnt<=0; else Bcd_min_one_cnt<=bcd_min_one_cnt+1;end
if (seg_flash_data_r[3]==1&key_value==8&key_flag==1) begin if (bcd_min_ten_cnt==5) bcd_min_ten_cnt<=0; else Bcd_min_ten_cnt<=bcd_min_ten_cnt+1;end End

2:begin bcd_seg_display_num_r[15:0] <= {bcd_hour_ten_cnt,bcd_hour_one_cnt,bcd_min_ten_cnt,bcd_min_one_cnt}; Seg_flash_data_r<=4 ' B0000;end



3:begin seg_flash_data_r<=4 ' b0001;
if (key_value==6&key_flag==1) seg_flash_data_r[3:0] <= {seg_flash_data_r[2:0],seg_flash_data_r[3]};
if (key_value==14&key_flag==1) seg_flash_data_r[3:0] <= {seg_flash_data_r[0],seg_flash_data_r[3:1]};
Bcd_seg_display_num_r[15:0] <= {bcd_hour_ten_cnt,bcd_hour_one_cnt,bcd_min_ten_cnt,bcd_min_one_cnt};
if (seg_flash_data_r[0]==1&key_value==13&key_flag==1) begin if (bcd_min_one_cnt==9) bcd_sec_one_cnt<=0; else Bcd_sec_one_cnt<=bcd_sec_one_cnt+1;end
if (seg_flash_data_r[1]==1&key_value==12&key_flag==1) begin if (bcd_min_ten_cnt==5) bcd_sec_ten_cnt<=0; else Bcd_sec_ten_cnt<=bcd_sec_ten_cnt+1;end
if (seg_flash_data_r[2]==1&key_value==5&key_flag==1) begin if (bcd_hour_one_cnt==9) bcd_hour_one_cnt<=0; else Bcd_hour_one_cnt<=bcd_hour_one_cnt+1;end
if (seg_flash_data_r[3]==1&key_value==4&key_flag==1) begin if (bcd_hour_ten_cnt==2) bcd_hour_ten_cnt<=0; else bcd_hour_ten_cnt<=bcd_hour_ten_cnt+1;endend*/











1:begin seg_flash_data_r<=4 ' b1000;
Bcd_seg_display_num_r[15:0] <= {bcd_hour_ten_cnt,bcd_hour_one_cnt,bcd_min_ten_cnt,bcd_min_one_cnt};
if (key_value==4&key_flag==1) begin if (bcd_hour_ten_cnt==2) Bcd_hour_ten_cnt<=0;else bcd_hour_ten_cnt<= Bcd_hour_ten_cnt+1;end End


2:begin
Seg_flash_data_r<=4 ' b0100;
Bcd_seg_display_num_r[15:0] <= {bcd_hour_ten_cnt,bcd_hour_one_cnt,bcd_min_ten_cnt,bcd_min_one_cnt};
if (key_value==5&key_flag==1) begin if (bcd_hour_one_cnt==9) Bcd_hour_one_cnt<=0;else bcd_hour_one_cnt<= Bcd_hour_one_cnt+1;end End

3:begin
Seg_flash_data_r<=4 ' b0010;
Bcd_seg_display_num_r[15:0] <= {bcd_hour_ten_cnt,bcd_hour_one_cnt,bcd_min_ten_cnt,bcd_min_one_cnt};
if (key_value==8&key_flag==1) begin if (bcd_min_ten_cnt==5) Bcd_min_ten_cnt<=0;else bcd_min_ten_cnt<=bcd_ Min_ten_cnt+1;end End

4:begin
Seg_flash_data_r<=4 ' b0001;
Bcd_seg_display_num_r[15:0] <= {bcd_hour_ten_cnt,bcd_hour_one_cnt,bcd_min_ten_cnt,bcd_min_one_cnt};
if (key_value==9&key_flag==1) begin if (bcd_min_one_cnt==9) Bcd_min_one_cnt<=0;else bcd_min_one_cnt<=bcd_ Min_one_cnt+1;end End


5:begin
Seg_flash_data_r<=4 ' b0010;
Bcd_seg_display_num_r[15:0] <= {bcd_min_ten_cnt,bcd_min_one_cnt,bcd_sec_ten_cnt,bcd_sec_one_cnt};
if (key_value==12&key_flag==1) begin if (bcd_sec_ten_cnt==5) Bcd_sec_ten_cnt<=0;else bcd_sec_ten_cnt<=bcd_ Sec_ten_cnt+1;end End


6:begin
Seg_flash_data_r<=4 ' b0001;
Bcd_seg_display_num_r[15:0] <= {bcd_min_ten_cnt,bcd_min_one_cnt,bcd_sec_ten_cnt,bcd_sec_one_cnt};
if (key_value==13&key_flag==1) begin if (bcd_sec_one_cnt==9) bcd_sec_one_cnt<=0; else Bcd_sec_one_cnt<=bcd_sec_one_cnt+1;end End
Default:begin Bcd_sec_one_cnt<=0;bcd_sec_ten_cnt<=0;bcd_min_one_cnt<=0;bcd_min_ten_cnt<=0;bcd_ Hour_one_cnt<=0;bcd_hour_ten_cnt<=0;end
Endcase
End
Assign seg_flash_data[3:0] = Flag_1s_r seg_flash_data_r[3:0]:4 ' b0000;
Assign bcd_seg_display_num[15:0] = bcd_seg_display_num_r[15:0];

Wire alarm = (bcd_hour_ten_cnt==1&&bcd_hour_one_cnt==2&&bcd_min_ten_cnt==0&&bcd_min_one_ cnt==0&&bcd_sec_ten_cnt==0&&bcd_sec_one_cnt==0);

reg [26:0]beep_count;

[Email protected] (Posedge CLK or Negedge rst_n)
Begin
if (!rst_n)
Begin
Beep_count <= 0;
End
else if (alarm)
Beep_count <= ' d125000000;
else if (beep_count>0)
Beep_count <= beep_count-1;

End

Assign Alarm_beep = (beep_count>0 && (beep_count[24]&& beep_count[14]) | | (~beep_count[24]&& beep_count[13]));
Endmodule

Display control Module

Module Seg595_control_module (Clk,rst_n,num1_ten_smg_data,num1_one_smg_data,num2_ten_smg_data,num2_one_smg_data, SEG_FLASH_DATA,DUAN_WEI_DATA,FLAG_1S,START_SIG,DONE_SIG);
Input CLK;
Input rst_n;
input [7:0] num1_ten_smg_data;
input [7:0] num1_one_smg_data;
input [7:0] num2_ten_smg_data;
input [7:0] num2_one_smg_data;
input [3:0] seg_flash_data;
Output [15:0]duan_wei_data;
Output Start_sig;
Input done_sig;
Input flag_1s;

Parameter t_1s=25000000;
Parameter t_1s=2500;

reg [15:0]duan_wei_data_r;
Reg Start_sig_r;
reg [3:0]state;

[Email protected] (Posedge CLK or Negedge rst_n)
Begin
if (!rst_n)
Begin
state<=0;
Start_sig_r <= 1 ' b0;
End
Else

Case (state)
0:
Begin duan_wei_data_r[15:0] <= {num2_one_smg_data,8 ' h27}; State <= State + 1; Start_sig_r <= 1 ' B1; End

1:
Begin Start_sig_r <= 1 ' b0; state<=4; End

2:
if (DONE_SIG) begin duan_wei_data_r[15:0] <= {(seg_flash_data[3]?8 ' h00:num2_ten_smg_data), flag_1s?8 ' H1e:8 ' h2e}; State <= State + 1; Start_sig_r <= 1 ' B1; end//{num2_ten_smg_data,4 ' H2, (4 ' he&seg_flash_data)}; State <= State + 1; Start_sig_r <= 1 ' B1; End

3:
Begin Start_sig_r <= 1 ' b0; State <= State + 1; End

4:
if (DONE_SIG) begin duan_wei_data_r[15:0] <= {(seg_flash_data[2]?8 ' h00:num2_one_smg_data), flag_1s?8 ' H1d:8 ' h2d}; State <= State + 1; Start_sig_r <= 1 ' B1; end//{num2_one_smg_data,4 ' H2, (4 ' hd&seg_flash_data)};state <= State + 1; Start_sig_r <= 1 ' B1; End

5:
Begin Start_sig_r <= 1 ' b0; State <= State + 1; End

6:
if (DONE_SIG) begin duan_wei_data_r[15:0] <= {(seg_flash_data[1]?8 ' h00:num1_ten_smg_data), flag_1s?8 ' H1b:8 ' H
b}; State <= State + 1; Start_sig_r <= 1 ' B1; end//{num1_ten_smg_data,4 ' H2, (4 ' hb&seg_flash_data)}; State <= State + 1; Start_sig_r <= 1 ' B1; End

7:
Begin Start_sig_r <= 1 ' b0; State <= State + 1; End

8:
if (DONE_SIG) begin duan_wei_data_r[15:0] <= {(seg_flash_data[0]?8 ' h00:num1_one_smg_data), flag_1s?8 ' H17:8 ' h27}; State <= State + 1; Start_sig_r <= 1 ' B1; end//{num1_one_smg_data,4 ' H2, (4 ' h7&seg_flash_data)}; State <= State + 1; Start_sig_r <= 1 ' B1; End

9:
Begin Start_sig_r <= 1 ' b0; state<=2; End

Default
Begin state <= 0;start_sig_r <= 1 ' b0; End
Endcase
End

Assign Start_sig = Start_sig_r;
Assign duan_wei_data = Duan_wei_data_r;
Endmodule

Display Module

Module Seg595_function_module (clk,rst_n,duan_wei_data,start_sig,done_sig,sck,rck,dout);
Input CLK;
Input rst_n;
input [15:0]duan_wei_data;
Input start_sig;
Output Done_sig;
Output sck;
Output Rck;
Output dout;

5M frequency

reg [2:0]count1;
Reg Sck_r;

Always @ (Posedge CLK or Negedge rst_n)
Begin
if (!rst_n)
Begin count1<=0; sck_r<=0; End
else if (count1 = = 3 ' D4)
Begin count1<=0; Sck_r = ~ Sck_r; End
else count1 <= count1 +1;
End




The entire falling edge pulse
Reg SCK_FLAG1;
Reg SCK_FLAG2;
Always @ (Posedge CLK or Negedge rst_n)
Begin
if (!rst_n)
Begin
Sck_flag1 <= 1 ' B1;
Sck_flag2 <= 1 ' B1;
End
Else
Begin
Sck_flag1 <= Sck_r;
Sck_flag2 <= Sck_flag1;
End
End

Wire Sck_negedge;

Assign sck_negedge= (Sck_flag2 && ~sck_flag1)? 1 ' b1:1 ' B0;

reg [6:0]state;
Reg Rck_r;
Reg Dout_r;
Reg Done_sig_r;

Each sck, falling edge into the data, rising edge to, input and output. Rck each of the 16 sck.

Always @ (Posedge CLK or Negedge rst_n)
Begin
if (!rst_n)
Begin
Dout_r <= 0;
State <= 0;
Done_sig_r <= 1 ' b0;
End
Else
Case (state)
0:if (start_sig) State <= State + 1;
1:if (Sck_negedge) begin Dout_r <= duan_wei_data[15]; Rck_r <= 1 ' B1; State <= State + 1; End
2:if (Sck_negedge) begin Dout_r <= duan_wei_data[14]; State <= State + 1; End
3:if (Sck_negedge) begin Dout_r <= duan_wei_data[13]; State <= State + 1; End
4:if (Sck_negedge) begin Dout_r <= duan_wei_data[12]; State <= State + 1; End
5:if (Sck_negedge) begin Dout_r <= duan_wei_data[11]; State <= State + 1; End
6:if (Sck_negedge) begin Dout_r <= duan_wei_data[10]; State <= State + 1; End
7:if (Sck_negedge) begin Dout_r <= duan_wei_data[9]; State <= State + 1; End
8:if (Sck_negedge) begin Dout_r <= duan_wei_data[8]; State <= State + 1; End
9:if (Sck_negedge) begin Dout_r <= duan_wei_data[7]; State <= State + 1; End
10:if (Sck_negedge) begin Dout_r <= duan_wei_data[6]; State <= State + 1; End
11:if (Sck_negedge) begin Dout_r <= duan_wei_data[5]; State <= State + 1; End
12:if (Sck_negedge) begin Dout_r <= duan_wei_data[4]; State <= State + 1; End
13:if (Sck_negedge) begin Dout_r <= duan_wei_data[3]; State <= State + 1; End
14:if (Sck_negedge) begin Dout_r <= duan_wei_data[2]; State <= State + 1; End
15:if (Sck_negedge) begin Dout_r <= duan_wei_data[1]; State <= State + 1; End
16:if (Sck_negedge) begin Dout_r <= duan_wei_data[0]; Rck_r <= 1 ' b0; State <= State + 1; Done_sig_r <= 1 ' B1; End
17:begin done_sig_r <= 1 ' b0; State <= 0; End

Default:begin dout_r <= 0; State <= 0; Done_sig_r <= 1 ' b0; End
Endcase
End

Assign Done_sig = Done_sig_r;
Assign dout = Dout_r;
Assign Rck = Rck_r;
Assign sck = Sck_r;

Endmodule

Digital Tube Decoding Module

Module Smg_encoder_module (clk,rst_n,num,smg_data);

Input CLK;
Input rst_n;
input [3:0]num;
Output [7:0]smg_data;

/* Common Cathode digital tube: Select the low level (that is, 0) selected digital tube, each segment selected as high level (i.e. 1 + +) selected each digital segment; */

The code from 0 to F is

Parameter
Seg_num0=8 ' h3f,

Seg_num1=8 ' h06,

Seg_num2=8 ' h5b,

Seg_num3=8 ' h4f,

Seg_num4=8 ' H66,

Seg_num5=8 ' h6d,

Seg_num6=8 ' h7d,

Seg_num7=8 ' h07,

Seg_num8=8 ' h7f,

Seg_num9=8 ' h6f,

Seg_numa=8 ' H77,

Seg_numb=8 ' h7c,

Seg_numc=8 ' H39,

Seg_numd=8 ' h5e,

Seg_nume=8 ' h79,

Seg_numf=8 ' h71;

reg [7:0]smg_data_r;

Always @ (Posedge CLK or Negedge rst_n)
Begin
if (!rst_n)
Smg_data_r <= 8 ' b00000000;
Else
Case (NUM)
4 ' D0:smg_data_r <= SEG_NUM0;
4 ' D1:smg_data_r <= seg_num1;
4 ' D2:smg_data_r <= seg_num2;
4 ' D3:smg_data_r <= seg_num3;
4 ' D4:smg_data_r <= seg_num4;
4 ' D5:smg_data_r <= SEG_NUM5;
4 ' D6:smg_data_r <= seg_num6;
4 ' D7:smg_data_r <= seg_num7;
4 ' D8:smg_data_r <= seg_num8;
4 ' D9:smg_data_r <= seg_num9;

Default:smg_data_r <= 8 ' b00000000;
Endcase
End

Assign Smg_data=smg_data_r;

Endmodule

Realization of digital clock realization and dynamic adjustable and alarm function