Relationship between blocked copy, non-blocking copy, sequential block, and Parallel Block

These concepts are different.
Ordered block: the statements in the ordered block are executed sequentially, and the delay value in each statement is related to the simulation time of the previous statement execution.
Parallel Block: Parallel Block statements are executed in parallel. The delay value specified in each statement is relative to the execution time of the statement block.
The difference between a sequential block and a parallel block is the simulation time of each statement in it, rather than the specific blocking or non-blocking statements.
Blocking assignment: This assignment statement must have been completed before the execution of the following statement.
Non-blocking assignment: When a non-obstructive assignment statement is executed, the expression on the right is calculated, and the value on the right is assigned to the target at a predetermined time. The fastest output is also the last time before the end of the current time. After it calculates the value on the right, it is not blocked, and the subsequent statements run normally, and the true value assignment occurs at the current or the end of the delay. It does not block subsequent statement execution. It is characteristic of assigning values at the current or delayed end time. The internal latency of subsequent statements only indicates the time when the value is assigned, rather than the time when the value is assigned. They are different concepts.

The following is an example of synplify_pro:

Module test (
D1,
CLK,
Q1,
Q2
);
Input D1, CLK;
Output Q1;
Output Q2;
Reg Q1, Q2;

Always @ (posedge CLK)
Begin
Q1 = D1;
Q2 = Q1;
End
Endmodule
After integration, there is only one DFF.

Module test (
D1,
CLK,
Q1,
Q2
);
Input D1, CLK;
Output Q1;
Output Q2;
Reg Q1, Q2;

Always @ (posedge CLK)
Fork
Q1 = D1;
Q2 = Q1;
Join
Endmodule

There are two DFF after integration.

 

Module test (
D1,
CLK,
Q1,
Q2
);
Input D1, CLK;
Output Q1;
Output Q2;
Reg Q1, Q2;

Always @ (posedge CLK)
Begin
Q1 <= D1;
Q2 <= Q1;
End
Endmodule
There are two DFF after integration.

 

Module test (
D1,
CLK,
Q1,
Q2
);
Input D1, CLK;
Output Q1;
Output Q2;
Reg Q1, Q2;

Always @ (posedge CLK)
Fork
Q1 <= D1;
Q2 <= Q1;
Join
Endmodule

There are two DFF after integration.

Relationship between blocked copy, non-blocking copy, sequential block, and Parallel Block