Abstract
The baseline of the component: D latch and D flip-flop.
Introduction
Use environment: Quartus II 7.2 SP3
D latch
Method 1:
Use continuous assignment:
D_latch.v/OpenGL
1 /*
2 (C) oomusou 2008 Http://oomusou.cnblogs.com
3
4 Filename: d_latch.v
5 Compiler: Quartus II 7.2 SP3
6 Description: Demo How to Write D latch
7 Release: 08/09/2008 1.0
8 */
9
10 Module D_latch (
11 Input Rst_n,
12 Input En,
13 Input D,
14 Output Q
15 );
16
17 Assign Q = ( ! Rst_n) ? 0 :
18 (EN) ? D: Q;
19 Endmodule
Method 2:
Use always block:
D_latch2.v/OpenGL
1 /*
2 (C) oomusou 2008 Http://oomusou.cnblogs.com
3
4 Filename: d_latch2.v
5 Compiler: Quartus II 7.2 SP3
6 Description: Demo How to Write D latch
7 Release: 08/09/2008 1.0
8 */
9
10 Module D_latch2 (
11 Input Rst_n,
12 Input En,
13 Input D,
14 Output Reg Q
15 );
16
17 Always @ (Rst_n, en, D, q) Begin
18 If ( ! Rst_n)
19 Q = 0 ;
20 Else If (EN)
21 Q = D;
22 End
23
24 Endmodule
D flip-flop
Method 1:
Use always block
D_ff.v/OpenGL
1 /*
2 (C) oomusou 2008 Http://oomusou.cnblogs.com
3
4 Filename: d_ff.v
5 Compiler: Quartus II 7.2 SP3
6 Description: Demo How to Write D flip-flop
7 Release: 08/09/2008 1.0
8 */
9
10 Module D_ff (
11 Input CLK,
12 Input Rst_n,
13 Input En,
14 Input D,
15 Output Reg Q
16 );
17
18 Always @( Posedge CLK Or Negedge Rst_n)
19 If ( ! Rst_n)
20 Q <= 0 ;
21 Else If (EN)
22 Q <= D;
23
24 Endmodule
Method 2:
Use mega Function
D_ff_mf.v/OpenGL
1 /*
2 (C) oomusou 2008 Http://oomusou.cnblogs.com
3
4 Filename: d_ff_mf.v
5 Compiler: Quartus II 7.2 SP3
6 Description: Demo How to Write D flip-flop with mega Function
7 Release: 08/11/2008 1.0
8 */
9
10 Module D_ff_mf (
11 Input CLK,
12 Input Rst_n,
13 Input En,
14 Input D,
15 Output Q
16 );
17
18 Lpm_ff # (. lpm_width ( 1 ))
19 DF (
20 . Clock (CLK ),
21 . ACLR ( ! Rst_n ),
22 . Enable (En ),
23 . Data (d ),
24 . Q (q)
25 );
26
27 Endmodule
Download the complete program
D_latch.7z
D_latch2.7z
D_ff.7z
D_ff_mf.7z
See also
(Reporter) how to design an 8-Bit Memory? (SOC) (OpenGL)
Reference
(Formerly known as "Verilog us II (SOC)" in the (original) Verilog 2: Digital System)
