Repost about incremental compilation

A few days ago, the teacher needed a design data. It was a compilation report for a large FPGA project module, the previous Small Module Project has no idea where it is (I also think it is not good here, although the module is small, it is also verified by careful design simulation at the beginning of the design, archiving should be done )...... Well, it doesn't matter if it's gone, but it's actually quite simple. Just copy the big project, top the sub-modules, and re-compile it.

After compilation, an error is reported! It's a bit confusing. At first, it was a bit confusing ......

Error: partition hierarchy "pn_gen: inst2" does not exist in the current design or refers to an inferred hierarchy
Error: partition hierarchy "ts_gen: inst5" does not exist in the current design or refers to an inferred hierarchy

Several errors are similar, which roughly means that the "*****" modules do not exist in the current design. I think it is strange here that the modules with errors are other sub-modules in the original project. Of course they are not included in the current design. How can I return an error ??

Double-click the red error and the system prompts no response, so right-click the error and choose "help:

The general meaning is that there is no entity for the set region division ...... We recommend that you delete or recreate the region. After reading it, it's still confusing ...... It should have been a very simple operation. How can this problem occur? First, let's calm down and think about it. Don't panic. To sum up this problem, I personally have the following information:

(1) double-click the red error and the system prompts no response, indicating that it is definitely not an error in the design file. It should be a compilation setting or the overall setting is incorrect;

(2) There is a keyword in the help and error prompts-"partition". The Chinese explanation is the meaning of Regional Division. I always think that I have seen it before, but I cannot think of it too much.

If the problem is caused by compilation settings, open the qsf file first! (Qsf is a command line file. The settings we perform on the Quartus software are written to this file in the form of commands.) Although most of the content may not be very familiar to you, it doesn't matter, you can use words and variables to roughly guess what a command is related. After opening it, I will see the following commands: (the figure below shows the comments)

Why did you notice this? Very simple: keyword partition, and the name of each module with errors. After analyzing these commands, I thought of them.At that time, due to the large project, it was set during logical region division during incremental compilation of Quartus.!

It is easy to find the error. Comment out this part of the command and compile it again.

This article does not introduce Quartus incremental compilation for the time being. I would like to summarize some of the analysis methods and procedures that should be followed when an error occurs.

First, after an error occurs, our first response will be to double-click the error prompt to see where it will jump ...... Indeed, this is the most direct method, and most problems in design can be solved through this method;

2. When you are not familiar with this error, you can right-click the error prompt-> help, and then the Altera's explanation of this type of error will pop up, however, all it can do is to explain this error type, but it is certainly impossible to explain it to your project;

Third, when you are not familiar with the error message content, you should see the "keyword" in it to narrow down the scope of our analysis;

4. Learn to view the command content of the qsf file. When there is no problem with the design file, it is likely that a command in it has caused your error;

Finally, haha, we all know that using network resources, there are a large number of scalpers on the Internet !! You cannot solve the problem. Someone must have encountered or solved it ~~

 

 

Next, let's take a closer look at this incremental compilation.

First, let's take a look at how the compilation process of quartuⅱ is. To understand this process, it is very easy. Look at the figure below. No one is familiar with it:

After all the compilation, the following processes are checked one by one, and the compilation process is consistent with the running process: first, analysis and synthesis, next, layout and wiring, and then assembly (this is not a compilation of assembly languages, but a compilation of the "circuit" after layout and wiring into a "program" that can be downloaded to the chip "), there are also Time Series Analysis and generation of network tables.

When we look at the compilation process, we will find that the most time-consuming part is the analysis and layout wiring (this can also be seen from the time Annotation on the right ), therefore, we should start from this point to increase the compilation speed.

Quartus also has related automatic incremental compilation settings, such:

The first is the multi-core processor settings, which can improve the overall speed; the second is the smart compilation, smart compilation method, which can complete the functions-if the design source file is not modified, then Quartus will not analyze and synthesize, but directly enter the layout and wiring stage. You can also select the following settings:

Rapid recompile, that is, if the design is not modified, it is not re-compiled.

From the compilation process, let's take a look at our design process:

We can find that the design process is the same as the compilation process. WhileThe principle of incremental compilation is to reduce the part we have designed in each compilation, so that we do not need to repeat what the designer thinks has been done.To put it bluntly, our designers have to manually divide the entire project into n sub-modules (logical modules) and set the status of each module (completed, if you do not need to change it, the last result is used during compilation.) in this way, the compiler can directly use the last result for those parts that do not need to be modified during analysis and synthesis. The layout and wiring are the same. If the sub-module does not need to be changed, the last result will be used. If you need to change the layout and wiring, however, the layout and wiring process is more complex than analysis.

As mentioned above, to manually divide the entire project into N modules, we need to use the two advanced tools provided by Quartus-design partitions and logiclock regions.

 

 

This article will take a closer look at how to use incremental compilation.

The two main tools used for incremental compilation are design partition and logiclock.

First, we need to propose a concept. Most of the online incremental compilation brief descriptions are: Using logiclock for incremental compilation. This is a wrong opinion!Logiclock is not part of incremental compilation. We recommend that you use logiclock during incremental compilation!

In addition, my personal understanding of the incremental compilation principle mentioned in the previous article: divide the entire project into multiple "logical regions ", in each compilation, the network Table type of each region is set to determine whether to re-execute this compilation, "incremental compilation" is an "incremental" process for the next compilation and previous compilation of the entire project during the design process. In fact, the official name of Altera should be called "progressive compilation mode ".

From the understanding of the principle, we can find that we only need to use design partition to complete "incremental compilation. The following describes how to use the design partition tool:

First, you have to perform a full compilation of the entire project (or do not compile it. You only need to analyze the top-level modules. If there are small icons marked on the left, you can open the sub-modules under the top-level analysis module ), during the analysis process, Quartus can automatically analyze the sub-modules contained in the top-level modules of the entire project;

Then, the child module is "logical partition" through design partition ". Generally, we can directly set the sub-modules analyzed in the previous step to "logical region ";

Open the design partition window after setting, as shown in the following figure:

Its structure is similar to that in project navigator. There is a top module, and the small areas we have set below. Each column parameter in the table is a setting for each region. The most critical setting is netlist type, which has four optional values: source file, post-synthesis, post-fit, empty (such as marked 1, 2, 3, 4 in the Chinese text, to fully display each type, rather than final setting ). Their respective meanings are:

Source File: if the source code is not modified, only analysis is performed again and synthesis and fitter are required;

Post-Synthesis: if the source code is not modified and you do not need to re-analyze or synthesis, the result will only be fitter;

Post-fit: if the source code is not modified, the results of the previous analysis, synthesis, and Fitter will be retained;

Empty: flag is an empty area. This partition is ignored during compilation.

So we can understand,In fact, to achieve the purpose of "incremental compilation", you only need to set each sub-module in design partition and set the modules that have not been modified to post-fit, the modified module is set to source file. Note that the top-level module status must also be set to post-fit.

You can try the results. The personal test results are remarkable ...... It takes more than five minutes to compile the program at a time. This method only takes more than one minute to change the content of one partition.

The use of logiclock will be further analyzed and discussed in subsequent articles.

 

 

Tragedy ...... Trip, just half the code ...... Re-code ......

Let's first clarify two concepts --"Logical partitions and physical partitions".

The design partition mentioned above only implements "logical partitioning" for the design. To put it bluntly, we divide our design into N small modules, each of which has its own logic and functions, it tells the compiler that this part of the logic is a partition A, that part of the logic is another partition B, after such a partition, the compiler does not change much in the overall project, layout and wiring. The logical partition is only used to let users know which part of the logic is partition, which part of the logic is partition B. Then, you can set the attribute types of partition a and partition B to tell the Compiler which part does not need to be integrated and layout and wiring, and which part has been modified, need to be integrated again and so on.

Let's take a look at the role of logiclock, which is to "physically partition" The design. More accurately, it is to "physically partition" the target device ", then, the functional modules in the logic are allocated to certain partitions. That is to say, we first divide the physical area of the target device into several "locations", and then select a logic function module to allocate it to a "location", telling the compiler, in the future, this part of logic functions can only be laid out in this "Site. Similarly, you can set the attributes of each module to tell the compiler in what form to layout and wiring in the "website.

The following is a brief introduction to the use of logiclock. We have previously used design partition for "logical partitioning". We can right-click the tree structure in the design using the same method, and then, for example:

Add each sub-module to logiclock region, as shown in the following figure:

There are two main parameters: Size and state: size. There are two options: auto and fixed, and State also has two options: Locked and floating. However, there are not four combinations, but there are only three states:

First, auto + floating: the compiler automatically selects the region size and position (displayed by dotted lines in the chip planner)

2. Fixed + floating: the location selected by the compiler, but the size of the region is set by the user. (It is displayed by the short line in the chip planner)

Third, fixed + locked: the size and location of the region are set by the user. (Display on chip planner by solid line)

So what is the role of logiclock in incremental compilation?You still need to emphasize that logiclock is not required for incremental compilation. However, we recommend that you use logiclock for incremental compilation!Why? Because it can make the idea of incremental compilation more thorough.

Let's think about the previous situation when we used design partition: The Logic Functions of the changed modules have greatly changed, which affects the layout and wiring of other "logical partitions, in this way, the unaltered part also needs to be re-compiled. However, if logiclock is used at this time, because each logic function module is assigned a certain "physical area ", the changed module is also in its own "Site" and will not affect the layout and wiring of other "sites.

However, logiclock also has a negative impact, which is the most direct. Generally, fmax after time series analysis is lower. Why? As a matter of fact, we can also know that if logiclock is not used, the compiler can automatically make major optimization from the global perspective, while we artificially limit physical partitions, even if each small module is well optimized, the layout and wiring between regions are limited, which naturally affects the layout. However, it cannot be absolutely determined that using this method can bring unexpected results if resources are used up to a large extent.

Repost about incremental compilation