[Reprinted] Important FPGA design ideas

1. Principle of speed and area interchange .. Changing the area speed can achieve high data throughput. In fact, string/and conversion is an idea of changing the area speed.

2. Ping-Pong operations

3. The thought of string/and conversion.

One of the important techniques for high-speed data processing. Here is an example of multi-phase filter extraction:

After extraction, the two data sources can be processed at a two-byte rate.

4. Pipeline Design (the FIR filter is very outstanding, and one clock outputs one data)

The pipeline design can increase the system frequency to some extent .. The premise is that the design can be divided into several steps for processing, and the entire data processing process is unidirectional, that is, there is no feedback or inverse operation, and the output of the previous step is the input of the next step...

3. Logical replication and module multiplexing are widely used in saving logical resources (for example, here). I will not talk about it much, but I would like to tell you a story! As for logical replication, we haven't met it yet. Copy the concept first: Logical replication is an optimization method to improve timing conditions by adding area. Its most important application is to adjust the fan-out of signals. In other words, that is, the fan output is very large, so in order to increase the drive capability of this signal, many levels of buffer must be inserted, which increases the path Delay of this signal to a certain extent. In this case, you can assign values to generate the logic of this signal, and use multiple signals of the same frequency and phase to drive the subsequent circuit, which is to decrease the average to the fan-out of each Luther King, in this way, you do not need to insert the buffer to meet the demand for increased driving capabilities, thus saving the path Delay of the signal. In short. Module reuse saves area and sacrifices speed, while logical replication is the opposite .. 5. modular design is a top-down design method .. If you don't discuss it, it's very easy. 6. Clock Design tips try to avoid using the clock generated by FPGA internal logic, because it can easily cause functional or timing problems. The clock generated by the internal combination logic is prone to glitches, which affects the implementation of the designed functions. The inherent delay of the combination logic also easily leads to timing problems. If the output produced by the internal combination logic is used as the clock signal or Asynchronous Reset signal, glitch may inevitably occur. If the signal is in the transformation process at this time, it will violate the requirements of the establishment time and retention time, thus affecting the output status of the subsequent circuit, and even cause the entire system to fail to run. If you want to reduce the glitch, you 'd better use the clock .. Achieve Synchronous processing. The enable clock should be used as much as possible for the clock to be used in the design, so that the enable signal can be used as the enable signal.

 

[Reprinted] Important FPGA design ideas