Reproduced [FPGA] How to use SIGNALTAP to observe wire and Reg values

Original link:http://www.cnblogs.com/oomusou/archive/2008/10/17/signaltap_ii_reg_wire.html

Abstract
When writing a Verilog, although each module is emulated with the simulator of Modelsim or Quartus II, it is true that some of the non-predictable "run-time" problems may be one by one when each module is merged. This is done by Signaltap II to help with Debug.

Introduction
Use of the environment: Quartus II 8.0 + de2-70 (Cyclone II ep2c70f896c6n)

When you actually use Signaltap II, you'll notice that some reg and wire can be observed, and some can't be observed, how do you use Signaltap II to observe reg values in (original)? (IC Design) (Quartus II) (Signaltap II) (Verilog), I use Reg to the top module to observe Reg, although feasible, but it is not a very good way to say. At the beginning of the Web-site review, it was because Reg was Quartus II, which led to the non-use of Signaltap II observation, this article compiled a complete reg and wire observation method.

Observing Reg
Like (original) how to use Signaltap II to observe the Reg value? (IC Design) (Quartus II) (Signaltap II) (Verilog) For example, I repeat again.

Ssignaltapii_register_not_preserve.v/verilog

1/*
2 (C) Oomusou http://oomusou.cnblogs.com
3
4 FILENAME:SIGNALTAPII_REGISTER_NOT_PRESERVE.V
5 Compiler:quartus II 8.0
6 Description:demo How to preserve register with Singaltap II
7 release:10/17/2008 1.0
8 */
9
Ten Module Signaltapii_register_not_preserve (
Input ICLK,
Input Irst_n
13);
14
-reg [3:0] CNT;
16
[Email protected] (Posedge iclk, Negedge irst_n) begin
if (!irst_n)
CNT <= 4 ' H0;
Else
CNT <= CNT + 4 ' H1;
End
23
Endmodule

This is a very simple calculator, I deliberately let CNT do not output, and want to use Signaltap II to observe the value of CNT this reg.

CNT is 0, obviously unreasonable, indicating the value of Signaltap II no capture CNT this reg . Why would this be?

If we remove Signaltap II, re-use Quartus II to observe its compilation report, which shows register as 0.

Observing the synthetic results of the RTL Viewer, there really is no register!!

This proves that one thing,Quartus II, when synthesized, found that CNT did not need output, and the self-optimizing non-synthetic CNT, led to Signaltap IIcan not observe the Reg, but sometimes for debugging convenience, we want to observe this kind of Reg, Is there a way for Quartus II not to activate the optimization?

Use synthesis attribute to avoid optimization

Signaltapii_register_preserve.v/verilog

1/*
2 (C) Oomusou http://oomusou.cnblogs.com
3
4 FILENAME:SIGNALTAPII_REGISTER_PRESERVE.V
5 Compiler:quartus II 8.0
6 Description:demo How to preserve register in Signaltap II
7 release:10/17/2008 1.0
8 */
9
Ten Module Signaltapii_register_preserve (
Input ICLK,
Input Irst_n
13)
14
reg [3:0] cnt/*synthesis noprune*/;
16
[Email protected] (Posedge iclk, Negedge irst_n) begin
if (!irst_n)
CNT <= 4 ' H0;
Else
CNT <= CNT + 4 ' H1;
End
23
Endmodule

15 rows

reg [3:0] cnt/*synthesis noprune*/;

More/*synthesis noprune*/This synthesis attribute, instructs Quartus II not to optimize for CNT, keep this register for SIGNALTAP II observation , Note that it must be written in front of the symbol, not in the following notation.

reg [3:0] cnt;/*synthesis noprune*///Wrong!!

After editing, Signaltap II will be able to observe the value of CNT!! The point is that you do not need to change the top module of the interface, just want to observe the Reg plus synthesis attribute can.

Quartus II also supports the linguistic approach of Verilog 2001

1/*
2 (C) Oomusou http://oomusou.cnblogs.com
3
4 FILENAME:SIGNALTAPII_REGISTER_PRESERVE.V
5 Compiler:quartus II 8.0
6 Description:demo How to preserve register in Signaltap II
7 release:10/17/2008 1.0
8 */
9
Ten Module Signaltapii_register_preserve (
Input ICLK,
Input Irst_n
13);
14
2001//Verilog
+//(*noprune*) reg [3:0] CNT;
17
[Email protected] (Posedge iclk, Negedge irst_n) begin
if (!irst_n)
CNT <= 4 ' H0;
+ Else
CNT <= CNT + 4 ' H1;
End
24
Endmodule

16 Rows

(*noprune*) reg [3:0] CNT;

This is the Verilog 2001 language, Quartus II 8.0 can also be read.

If you want the entire module of Reg is not optimized, you can put synthesis attribute in the module.

1/*
2 (C) Oomusou http://oomusou.cnblogs.com
3
4 FILENAME:SIGNALTAPII_REGISTER_PRESERVE.V
5 Compiler:quartus II 8.0
6 Description:demo How to preserve register in Signaltap II
7 release:10/17/2008 1.0
8 */
9
Ten Module Signaltapii_register_preserve (
Input ICLK,
Input Irst_n
/*synthesis noprune*/;
14
-reg [3:0] CNT;
16
[Email protected] (Posedge iclk, Negedge irst_n) begin
if (!irst_n)
CNT <= 4 ' H0;
Else
CNT <= CNT + 4 ' H1;
End
23
Endmodule

13 rows

Module Signaltapii_register_preserve (
Input ICLK,
Input Irst_n
//);
)/*synthesis noprune*/;

Put/*synthesis noprune*/in module, so that the whole module's reg will not be optimized, no more one by one designations.

Another reg-related synthesis attribute:/*synthesis preserve*/
Reg-related attribute, in addition to/*synthesis noprune*/available, there is a/*synthesis preserve*/available, the difference between the two:

/*synthesis noprune*/ avoid Quartus II to reduce the output of Reg.

/*synthesis preserve*/ avoid Quartus II to be an advantage of Reg, or merge the duplicate Reg.

You can also use the Verilog 2001 notation

(*preserve*) reg [3:0] CNT;

or the whole module notation.

Module Signaltapii_register_preserve (
Input ICLK,
Input Irst_n
)/*synthesis preserve*/;

Observing Wire
Similarly, in the SIGNALTAP II observation of the wire, sometimes it is also because the Quartus II is an advantage and can not be observed with Signaltap II.

Signaltapii_wire_not_keep.v/verilog

1/*
2 (C) Oomusou http://oomusou.cnblogs.com
3
4 FILENAME:SIGNALTAPII_WIRE_NOT_KEEP.V
5 Compiler:quartus II 8.0
6 Description:demo How to keep wire
7 release:10/17/2008 1.0
8 */
9
Ten Module Signaltapii_wire_not_keep (
Input ICLK,
Input Irst_n,
Output [3:0] ocnt
14);
15
[3:0] Cnt;
-reg [3:0] CNT;
18
Assign CNT = CNT;
Assign ocnt = Cnt;
21st
[Email protected] (Posedge iclk, Negedge irst_n) begin
if (!irst_n)
4 ' H0 of CNT <=;
-Else
CNT <= CNT + 4 ' H1;
End
28
Endmodule

16 Rows

Wire [3:0] Cnt;

I want to use Signaltap II to observe the CNT wire.

CNT is 0, obviously unreasonable, indicating the value of the SIGNALTAP II no capture CNT wire. Why would this be?

Because CNT this wire has been Quartus II by the superiority of the!!

But sometimes for the convenience of debug, we just want to watch this wire, is there a way for Quartus II not to activate optimization?

Signaltapii_wire_keep.v/verilog

1/*
2 (C) Oomusou http://oomusou.cnblogs.com
3
4 FILENAME:SIGNALTAPII_WIRE_KEEP.V
5 Compiler:quartus II 8.0
6 Description:demo How to keep wire
7 release:10/17/2008 1.0
8 */
9
Ten Module Signaltapii_wire_keep (
Input ICLK,
Input Irst_n,
Output [3:0] ocnt
14);
15
[3:0] Cnt/*synthesis keep*/;
-reg [3:0] CNT;
18
Assign CNT = CNT;
Assign ocnt = Cnt;
21st
[Email protected] (Posedge iclk, Negedge irst_n) begin
if (!irst_n)
4 ' H0 of CNT <=;
-Else
CNT <= CNT + 4 ' H1;
End
28
Endmodule

16 Rows

Wire [3:0] Cnt/*synthesis keep*/;

More/*synthesis keep*/This synthesis attribute, instructs Quartus II not to optimize CNT, retain this wire for SIGNALTAP II observation , Note that it must be written in front of the symbol, not in the following notation.

Wire [3:0] cnt;/*synthesis keep*///Wrong

After editing, Signaltap II will be able to observe the value of CNT!! The point is that you do not need to change the top module of the interface, just want to observe the wire plus synthesis attribute can.

Quartus II also supports the linguistic approach of Verilog 2001

1/*
2 (C) Oomusou http://oomusou.cnblogs.com
3
4 FILENAME:SIGNALTAPII_WIRE_KEEP.V
5 Compiler:quartus II 8.0
6 Description:demo How to keep wire
7 release:10/17/2008 1.0
8 */
9
Ten Module Signaltapii_wire_keep (
Input ICLK,
Input Irst_n,
Output [3:0] ocnt
14);
15
+//Verilog 2001
(*keep*) wire [3:0] Cnt;
reg [3:0] CNT;
19
Assign CNT = CNT;
Assign ocnt = Cnt;
22
[Email protected] (Posedge iclk, Negedge irst_n) begin
if (!irst_n)
CNT <= 4 ' H0;
+ Else
CNT <= CNT + 4 ' H1;
End
29
Endmodule

17 Rows

(*keep*) wire [3:0] Cnt;

This is the Verilog 2001 language, Quartus II 8.0 can also be read.

The current Quartus II 8.0 does not support/*synthesis keep*/under the whole module, the reason is unclear, I actually use Quartus II 8.0 test, SIGNALTAP II is not, and quartus II's help does not say it can be/*synthesis keep*/the entire module.

Conclusion
About Avoiding Quartus II reg,/*synthesis noprune*/and/*synthesis preserve*/There are some differences, the program is written to a very large time, it may be difficult to decide which attribute to use, alternately try to see, anyway 1 /2 chance, always on one.

After the use of synthesis attribute, the total solution is long enough to be used Signaltap II to observe the Reg and wire of the old problem, thank the Web Friends of the guiding.

Reproduced [FPGA] How to use SIGNALTAP to observe wire and Reg values