Research on interrupt Mechanism Based on PCI Bus

Abstract: The PCI bus has the plug-and-play (PNP, Plug and Play) feature, which makes the mechanism of CPU access to the expansion card significantly different from that of the plug-and-play system, particularly, the interrupt mechanism is complicated. This paper introduces in detail the interrupt Structure of High-performance PC and the interrupt mechanism of plx9052, and takes the PCI expansion card 9052 designed as the interface chip as an example, the program design points of data exchange between interrupt mode and CPU are discussed, aiming to fully understand the Interrupt Processing Mechanism Based on PCI Bus from the bottom layer, it provides theoretical basis and programming guidance for the design and implementation of the interrupt function of the PCI expansion card.
Keywords: PCI bus; plx9052; plug-and-play (PNP); interrupt

1 Overview
High-performance PCs generally use PCI bus as the system bus. Because the PCI bus protocol is complex, dedicated PCI interface chips are often used in the development of PCI expansion cards. Common PCI interface chips include the s59xx series of AMCC and plx905x series of PLX, among which plx9052 (hereinafter referred to as 9052) is widely used.
In application development, interruption is often used as a way to exchange data between the CPU and peripherals. However, because the PCI bus has the plug-and-play feature, that is, the memory space, I/O space, and interrupt resources of the PCI device are automatically configured, the mechanism of the CPU access expansion card is significantly different from that of the non-plug-and-play system, especially the interrupt mechanism.
If the PCI expansion card is designed based on the 9052 interface chip to exchange data with the CPU by means of hardware interruption, the process can be summarized into the following four steps, see Figure 1.

① If the external interrupt source connected to linti [] of the 9052 local interrupt input pin is valid and 9052 is enabled internally, the 9052 interrupt output signal INTA # is valid, this produces PCI interrupt requests.
② During power-on, the initialization software has automatically introduced the PCI interrupt to an interrupt pin (irqi) of the system interrupt controller based on the resource usage, and write the information into the configuration space of 9052. You can use the configuration space to obtain the configuration information.
③ If the interrupt request on irqi is not blocked and its level is high enough, the interrupt can be submitted to the CPU through the system interrupt controller.
④ If the CPU is currently interrupted, the response is interrupted and the interrupted service routine is entered for data exchange.
Therefore, to implement the interrupt function of the PCI expansion card, you need to understand not only the interrupt structure of the high-performance PC, but also the configuration space and interrupt mechanism of the PCI interface chip. This article first introduces the interrupt structure, 9052 configuration space and interrupt mechanism of high-performance PCs, and then provides the program design points for implementing data exchange between CPU and PCI expansion cards in an interrupt mode.

2. Interrupt structure of a high-performance PC [1]

The chipset is the soul of the motherboard. Some Motherboard chipset consists of North Bridge and South Bridge. In addition to conventional functions, the high-performance nanqiao chip also provides I/O interfaces for microcomputer systems, such as interrupt controllers and DMA controllers. For this reason, this article also called the Southern bridge as SiO2 (system I/O ). Different nanqiao chips have different complexity and extended functions of interrupt control logic. However, to maintain compatibility, the two-level interrupt controller is still consistent with the original PC/AT microcomputer.
2.1 SiO2 Interrupt Controller
As shown in figure 1, the "system interrupt controller" is an I/O interface integrated into the SiO2 for interrupt management. In this paper, it is called the SiO2 interrupt controller. Its minimum structure is shown in figure 2. Each 82c59 supports eight interrupt sources. The ir2 of the master and intr of the slave are connected, and 15 blocked interrupt sources are supported. The input source numbers of the Master are irq0 ~ Irq7, input source number of the slave slice is irq8 ~ Irq15.
After an external interrupt source sends a request to 82c59, the final optimization logic is used to determine the optimal interrupt level. If the request has the optimal interrupt level, the request is initiated to interrupt the source through its intr pin. When the CPU receives the request and the request is interrupted, the response is interrupted and the user's interrupt service routine is entered.
The two 82c59 integrated in the SiO2 still have all the registers of the original 82c59, and the functions and formats of each register remain unchanged. However, many optional functions of 82c59 In the SiO2 interrupt controller are fixed, cannot be rewritten through a program.
2.2 how to incorporate PCI interruptions into the system interrupt Structure
There are four interrupt request signal lines on the PCI bus: INTA #, intb #, intc #, and intd #, all are open and low-level (the corresponding irqi should be programmed as level trigger mode ). A single-function PCI device can only use one central disconnection (INTA #), and a multi-function PCI device can use other central disconnection according to PCI specifications. You can input four PCI interrupts into the SIO and direct them to an appropriate interrupt source based on the resource usage during power-on initialization. In this way, the PCI interrupt can be raised to the CPU through the system's shielded interrupt request.
3. configuration space and interrupt mechanism of plx9052
3.1 PCI device configuration space [1]
Each PCI device has a configuration space, each of which is called a configuration register. The configuration space of each PCI device includes the header area. The definition of the first 16 bytes in the header area is the same for all PCI devices. The configuration register at 0eh provides the header type, and 01 H is used for the main bridge, 00 h is used for other PCI devices. The layout of the 00h Type Header area is shown in figure 3.

The configuration space is the information exchange zone between the hardware of the PCI device and the initialization software and error handling software of the PCI device. With this information exchange zone, the PCI device can reflect its status and requirements to the software, and the software can identify, configure, and control the PCI device. During power-on, the initialization software first reads the relevant content in the configuration space to determine whether the PCI expansion card has been installed and the I/O space and MEM space required by the expansion card, then, the system automatically configures parameters such as the Basic address of the I/O space and MEM space, and the interrupt number occupied by the expansion card based on the system resource status. When the CPU needs to access the memory address or I/O port address on the expansion card, it only needs to obtain the corresponding base address from the configuration space and add the address offset.
3.2 plx9052 configuration space [2]
Since the header type field of 9052 is hard-coded as 0, the layout of the header area is the same as that shown in Figure 3. The 3ch offset of the header area is the disconnection register. The value is automatically configured when the system is powered on, indicating which input of the 9052 interrupt pin INTA # is connected to the system interrupt controller. By querying this register, you can understand the interrupt number assigned by the system to the PCI expansion card. The 3DH offset is the interrupt pin register, and its value indicates which interrupt pin is used by the PCI device. The relationship is 1-inta #, 2-intb #, 3-intc #, and 4-intd #. Because 9052 is a single-function device, it only supports INTA # One Interrupt, only when the value of this register is set to 1, the initialization software will direct INTA # To an irqi of the system interrupt controller.
9052 there is also a local configuration space for configuration and management of 9052. The base address register 9052 In the 0/1 header area is fixed to map the local configuration space of 9052 in memory or I/O mode. The PCI master device (such as the CPU) can read or modify the corresponding local configuration register through the base address in base address register 0/1 plus the offset of the local configuration register.
In the local configuration space, the registers with an offset of 4 ch are the interrupt control/Status Register intcsr, which is used to control the 9052 interrupt and provide relevant status information.
3.3 plx9052 interrupt mechanism [2]

As shown in intcsr format 4 of 9052, except that the Reserved Bit and linti status bit are read-only, the other bits are read/write bits.
· Linti enable bit: "1" allows linti to be interrupted; otherwise, it is forbidden.
· Linti valid level bit: When the level trigger mode is adopted, the value "1" indicates that the linti high level of the local interrupt input is valid; otherwise, the low level is valid.
· Linti status bit: "1" indicates that the source linti is valid; otherwise, it is invalid.
· PCI interrupt enable bit: "1" allows 9052 to generate PCI interrupt; otherwise, disable.
· Software interrupt bit: When the PCI interrupt enable bit is "1", the base write "1" will produce PCI interrupt.
· Linti trigger mode bit: "1" indicates that the rising edge is triggered, and "0" indicates that the level is triggered. The default value is the level trigger mode.
· Linti edge-triggered interrupt clearing bits: When linti generates a PCI interrupt in edge-triggered mode, the standard write "1" can be cleared.
· ISA mode enable bit (can only be loaded through serial E2PROM): Set "1" to allow ISA mode; otherwise, disable.
As we can see from the above, 9052 provides two types of interrupt sources: ① hard interrupt source. The linti [2: 1] pin is valid and is not forbidden. ② soft interrupt source. It is generated by setting the software interrupt bit in intcsr. A pci interrupt can be generated only when any interrupt source is valid and the PCI interrupt is enabled.
4. interrupt handling process and programming highlights [3]
In the Win9x environment, you usually need to use device drivers to access hardware resources. VtoolsD is a common third-party VxD device driver development tool. The following uses VC ++ 6.0 as the development environment, combined with the VtoolsD tool and the interrupt mechanism discussed in this article to introduce the key points of interrupt processing program development.
4.1 main program compilation points

Figure 5 main program process of interrupt handling

The initialization of the interruption should be completed in the main program. The process is shown in Figure 5. Pay attention to the following points during compilation:
① Obtain configuration Resources
If a new device is found during system initialization, Win9x sends the pnp_new _ devnode message. In this case, VxD can use functions such as configmg_register_device_driver and configmg_get_alloc_log_conf to obtain the configuration resources of the PCI device, add the configuration information to a structure config of cmconfig.
② Set the interrupt vector
From config, you can obtain the interrupt number IRQ configured for 9052, store the original interrupt vector, and set the interrupt vector to point to the user's interrupt service routine, so that the CPU automatically enters the user's Interrupt Processing subroutine in response to the interruption.
VtoolsD provides the vsharedhardwareint class to implement hardware interrupt processing. You can generate the mic_ioint class from the class. The onsharedhardwareint member function is your Interrupt Processing subroutine.

③ 9052 interruption allowed
You can program 9052 intcsr registers to enable 9052 interrupt generation. Assume that the application system uses the rising edge of 9052 linti2 to interrupt, the Code is as follows:

④ Corresponding bits of the open interrupt shield register
When an External Interrupt event is not blocked by 82c59 and has a high priority, an interrupt request can be sent to the CPU. Therefore, the corresponding interrupt shielding of 82c59 must be removed before the CPU is interrupted. This can be implemented using the physicalunmask () function in the vsharedhardwareint class.
4.2 Main Points of subroutine writing
The process of the interrupt processing subroutine is shown in Step 6. When writing Interrupt Processing subprograms, pay attention to the following two points:
① 9052 interrupted
Because the PCI interrupt is a level detection, when it receives a response, it should promptly cancel its request to avoid a second interruption, this can be achieved by writing 1 to intcs bit 11. The Code is as follows:

② Clear the corresponding interruption mark of the PC
Before the interruption is returned, or when the interruption priority can be dynamically changed after the interruption subprogram is entered, issue the interrupt Stop command to 82c59 to clear the corresponding interruption flag of the PC. If the interrupt is from the master chip, only the end command is sent to the master chip. If the interrupt is from the slave chip, the end command is sent to the master chip and the slave chip respectively. This can be implemented using the sendphysicaleoi () function in the vsharedhardwareint class.
5 conclusion
This paper systematically introduces the Interrupt Processing Mechanism Based on PCI Bus from the perspective of the combination of computer hardware and software, and gives the development points of the interrupt processing program, it can be of great help to computer hardware or software developers.
References
1 Ma mingjin, Zhao qiuxia, Zeng Guangyu. High-Performance PC hardware structure and interface [M]. Beijing: National Defense Industry Press, 2001.
2 PLX technology, Inc. PCI9052 data book version 2.0 [Eb/Ol]. http://www.plxtech.com./September 2001.
3 [us] Jon Bates, by Tim Tompkins, translated by Shi Xiangsheng. Visual C ++ 6 User Guide [M]. Beijing: Electronics Industry Press, 1999.

Reference address: www.2beanet.com/bbs http://www.2beanet.com/