S3C2440 bare metal learning [2]-LCD Driver principle and code analysis [1]

1. Hardware requirements for LCD:

To make an LCD display of text or images normally, not only the LCD driver, but also the corresponding LCD controller. Generally, the manufacturer makes the LCD driver in the form of cof/COG together with the LCD glass substrate, while the LCD controller is implemented by an external circuit, at present, many MCU are integrated with LCD controllers, such as S3C2410/2440. Through the LCD controller, the control signals required by the LCD driver can be generated to control the STN/tftscreen.

 

2. Structure of the internal LCD controller of S3C2440:

We will describe the LCD controller integrated in the S3C2440 according to the Data Manual:

A: The LCD controller consists of regbank, lcdcdma, timegen, and vidprcs registers;

B: regbank consists of 17 programmable Register Groups and a 256*16 color palette memory, which are used to configure the LCD controller;

C: lcdcdma is a dedicated DMA, which can automatically transmit video data in the memory to the LCD driver. By using this DMA channel, the video data is displayed on the LCD screen without CPU intervention;

D: vidprcs receives data from lcdcdma and converts the data to a suitable data format. For example, the 4/8-bit single scan mode and the 4-bit double scan mode are used, then, the video data is transmitted to the LCD driver through the data port VD;

E: timegen is composed of programmable logic that generates the control signals required by the LCD driver, such as vsync, hsync, vclk, and lend, these control signals are closely related to the configuration of lcdcon1, 2/3, and 4/5 in the regbank register group. With different configurations, timegen can generate different types of these signals, to support different LCD drivers (that is, different STN/tftscreen ).

3. Common tftscreen timing analysis:

External interface signals provided by LCD:

Vsync/vframe/STV:Vertical Synchronous signal (TFT)/frame synchronous signal (STN)/sec TFT signal; Hsync/vline/CPV:Horizontal synchronous signal (TFT)/Synchronous pulse signal (STN)/sec TFT signal; Vclk/LCD _hclk:Pixel clock signal (TFT/STN)/sec TFT signal; VD [23: 0]:LCD pixel data output port (TFT/STN/sec TFT ); Vden/Vm/TP:Data enabling signal (TFT)/LCD Drive AC offset signal (STN)/sec TFT signal; Lend/something:Line End signal (TFT)/sec TFT signal; LCD _lpcoe:Sec tft oe signal; LCD _lpcrev:Sec tft rev signal; LCD _lpcrevb:Sec tft revb signal.

 

The principle of displaying images on all displays is from top to bottom, from left to right. What does this mean? In this case, an image can be seen as a rectangle consisting of many neatly arranged vertices and rows. These vertices are called pixels. The display principle of this image on the LCD is:

A:The display pointer starts from the first point in the first line in the upper left corner of the rectangle. A point and a point are displayed on the LCD. In the time sequence diagram above, the time series are represented as vclk, which is called a pixel clock signal; B:When the display pointer is always displayed on the right side of the rectangle, the action of this row is called 1 line in the above sequence diagram; C:Next, we will display the pointer back to the left of the rectangle and start from the second line. Note that it takes some time to display the pointer back to the left of the second line from the right of the first line, we call it row switching; D:And so on, the display pointer shows a line to the bottom right corner of the rectangle. Therefore, the display of this row on the timeline is hsync on the timeline; E:However, the LCD display is not a quick display of a pair of images. To achieve continuous and stable display on the LCD, you need to switch to another image (the other image can be the same or different from the previous image, only to continuously display the image on the LCD ). Therefore, this image is called a frame, which is expressed as a frame in the sequence diagram. Therefore, from the sequence diagram, we can see that 1 line is only one row in 1 frame; F:Similarly, frame switching also takes some time. We call it frame switching. The entire LCD display process is displayed on the time line, it can be expressed as vsync on the sequence chart.

 

The meanings of clock delay parameters in the above sequence diagram are as follows: (for the values of these parameters, LCD manufacturers will provide corresponding data manuals)

Vbpd (vertical back porch ):Indicates the number of invalid lines after the vertical synchronization signal at the beginning of an image, corresponding to upper_margin in the drive; Vfbd (vertical front porch ):Indicates the number of invalid lines before the vertical synchronization signal after an image ends, corresponding to lower_margin in the driver; Vspw (vertical sync pulse width ):The width of the Vertical Synchronous pulse, calculated by the number of rows, corresponding to vsync_len in the driver; Hbpd (horizontal back porch ):Indicates the number of vclks between the start of the Horizontal synchronization signal and the start of a row of valid data, corresponding to left_margin in the driver; Hfpd (horizontal front Porth ):Indicates the number of vclks between the end of a row of valid data and the start of the next Horizontal synchronization signal, corresponding to right_margin in the driver; Heat map (horizontal sync pulse width ):The width of the horizontal synchronous signal. It is calculated using vclk and corresponds to hsync_len in the driver;

 

The values of the preceding parameters will be saved to the lcdcon1/0/0/2/3 registers in the regbank register group respectively. (For details about the operation on registers, see the LCD section of the S3C2440 Data Manual)

Lcdcon1: 17-8-bit clkval 6-5-bit scan mode (for the STN screen: 4-bit single/double scan, 8-bit single scan) 4-1-bit color (1bpp, 8bpp, 16bpp, etc) Lcdcon2: 31-24-bit vbpd 23-14-bit lineval 13-6-bit vfpd 5-0-bit vspw Lcdcon3: 25-19-bit hbpd 18-8-bit hozval 7-0-bit hfpd Lcdcon4: 7-0-bit hspw Lcdcon5:

 

4. Frame Buffer ):

Frame buffering is an interface provided by Linux for display devices. It describes some display devices as a buffer and allows applications to access these graphic devices through the interface defined in framebuffer, therefore, you do not need to care about specific hardware details. For frame buffering devices, the corresponding color is automatically displayed on the screen as long as the color value is written in the area corresponding to the display buffer and display point. Next, let's take a look at the relationship between the buffer and the display point in different color bit modes:

Above is from http://blog.chinaunix.net/u3/101649/showart_2188364.html
The operating principle of tft LCD is briefly described.